max_atoms.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 1,251 行 · 第 1/5 页
VHD
1,251 行
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_dataout := padio_ipd;
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
else
tmp_dataout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
else
tmp_padio := datain_ipd;
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- MAX_IO
--
library IEEE, max;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use max.atom_pack.all;
entity max_io is
generic ( operation_mode : string := "input";
open_drain_output :string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in std_logic := '0';
oe : in std_logic := '1';
devoe : in std_logic := '0';
dataout : out std_logic;
padio : inout std_logic);
end max_io;
architecture structure of max_io is
signal data_out : std_logic;
component max_asynch_io
generic ( operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
padio : inout STD_LOGIC;
dataout: out STD_LOGIC);
end component;
begin
asynch_inst: max_asynch_io
generic map ( operation_mode => operation_mode,
bus_hold => bus_hold,
open_drain_output => open_drain_output,
weak_pull_up => weak_pull_up)
port map ( datain => datain,
oe => oe,
padio => padio,
dataout => data_out);
dataout <= data_out;
end structure;
--
-- MAX MCELL Model
--
--
library IEEE, max;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use max.atom_pack.all;
entity max_asynch_mcell is
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pterm0_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pxor_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_combout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_fpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pxor_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_pexpout : VitalDelayType01 := DefPropDelay01;
tipd_pterm0 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm1 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm2 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm3 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm4 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm5 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pxor : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_fpin : VitalDelayType01 := DefPropDelay01;
tipd_pexpin : VitalDelayType01 := DefPropDelay01);
port ( pterm0 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm1 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm2 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm3 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm4 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm5 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
fpin : in std_logic := '1';
pxor : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pexpin : in std_logic := '0';
fbkin : in std_logic;
combout : out std_logic;
regin : out std_logic;
pexpout : out std_logic );
attribute VITAL_LEVEL0 of max_asynch_mcell : entity is TRUE;
end max_asynch_mcell;
architecture vital_mcell of max_asynch_mcell is
attribute VITAL_LEVEL0 of vital_mcell : architecture is TRUE;
signal pterm0_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm1_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm2_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm3_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm4_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm5_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal fpin_ipd :std_ulogic := 'U';
signal pxor_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pexpin_ipd :std_ulogic := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (pterm0_ipd(0), pterm0(0), tipd_pterm0(0));
VitalWireDelay (pterm0_ipd(1), pterm0(1), tipd_pterm0(1));
VitalWireDelay (pterm0_ipd(2), pterm0(2), tipd_pterm0(2));
VitalWireDelay (pterm0_ipd(3), pterm0(3), tipd_pterm0(3));
VitalWireDelay (pterm0_ipd(4), pterm0(4), tipd_pterm0(4));
VitalWireDelay (pterm0_ipd(5), pterm0(5), tipd_pterm0(5));
VitalWireDelay (pterm0_ipd(6), pterm0(6), tipd_pterm0(6));
VitalWireDelay (pterm0_ipd(7), pterm0(7), tipd_pterm0(7));
VitalWireDelay (pterm0_ipd(8), pterm0(8), tipd_pterm0(8));
VitalWireDelay (pterm0_ipd(9), pterm0(9), tipd_pterm0(9));
VitalWireDelay (pterm0_ipd(10), pterm0(10), tipd_pterm0(10));
VitalWireDelay (pterm0_ipd(11), pterm0(11), tipd_pterm0(11));
VitalWireDelay (pterm0_ipd(12), pterm0(12), tipd_pterm0(12));
VitalWireDelay (pterm0_ipd(13), pterm0(13), tipd_pterm0(13));
VitalWireDelay (pterm0_ipd(14), pterm0(14), tipd_pterm0(14));
VitalWireDelay (pterm0_ipd(15), pterm0(15), tipd_pterm0(15));
VitalWireDelay (pterm0_ipd(16), pterm0(16), tipd_pterm0(16));
VitalWireDelay (pterm0_ipd(17), pterm0(17), tipd_pterm0(17));
VitalWireDelay (pterm0_ipd(18), pterm0(18), tipd_pterm0(18));
VitalWireDelay (pterm0_ipd(19), pterm0(19), tipd_pterm0(19));
VitalWireDelay (pterm0_ipd(20), pterm0(20), tipd_pterm0(20));
VitalWireDelay (pterm0_ipd(21), pterm0(21), tipd_pterm0(21));
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?