📄 mercury_components.vhd
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tpd_fbin_clk2 : VitalDelayType01 := DefPropDelay01;
tpd_fbin_extclk : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_fbin : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01
);
PORT (clk : in std_logic;
ena : in std_logic := '1';
fbin : in std_logic := '1';
clk0 : out std_logic;
clk1 : out std_logic;
clk2 : out std_logic;
extclk : out std_logic;
locked : out std_logic
);
END COMPONENT;
COMPONENT mercury_cam_slice
GENERIC (operation_mode : string := "single_match";
logical_cam_name : string := "cam_xxx";
logical_cam_depth : integer := 64;
logical_cam_width : integer := 32;
address_width : integer := 6;
waddr_clear : string := "none";
write_enable_clear : string := "none";
write_logic_clock : string := "none";
write_logic_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
init_file : string := "xxx";
init_filex : string := "xxx";
first_address : integer := 0;
last_address : integer := 63;
first_pattern_bit : integer := 0;
pattern_width : integer := 32;
power_up : string := "low";
init_mem_true : mercury_mem_data := (OTHERS => "11111111111111111111111111111111");
init_mem_comp : mercury_mem_data := (OTHERS => "11111111111111111111111111111111")
);
PORT (clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
we : in std_logic := '0';
datain : in std_logic := '0';
wrinvert : in std_logic := '0';
outputselect : in std_logic := '0';
waddr : in std_logic_vector(5 downto 0);
lit : in std_logic_vector(31 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
modesel : in std_logic_vector(9 downto 0) := (OTHERS => '0');
matchout : out std_logic_vector(31 downto 0);
matchfound : out std_logic
);
END COMPONENT;
COMPONENT mercury_hssi_transmitter
GENERIC (
channel_width : integer := 20;
check_violation : String := "true";
operation_mode : String := "LVDS";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_negedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_negedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk_clkout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(19 downto 0) := (
OTHERS => DefpropDelay01));
PORT (
clk : in std_logic;
areset : in std_logic := '0';
datain : in std_logic_vector(19 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
clkout : out std_logic;
dataout : out std_logic);
END COMPONENT;
COMPONENT mercury_hssi_receiver
GENERIC (
channel_width : integer := 20;
operation_mode : String := "LVDS";
run_length : integer := 1;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_negedge: VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_clkout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rlv_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk_locked_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_feedback : VitalDelayType01 := DefpropDelay01;
tipd_fbkcntl : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01);
PORT (
clk : in std_logic;
coreclk : in std_logic := '0';
datain : in std_logic;
areset : in std_logic := '0';
feedback : in std_logic := '0';
fbkcntl : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
clkout : out std_logic;
rlv : out std_logic;
locked : out std_logic;
dataout : out std_logic_vector(19 downto 0));
END COMPONENT;
COMPONENT mercury_hssi_pll
GENERIC (clk0_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
input_frequency : integer := 1000;
clkin_settings : string := "";
clk0_settings : string := "";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01
);
PORT (clk : in std_logic := '0';
areset : in std_logic := '0';
clk0 : out std_logic;
clk1 : out std_logic;
locked : out std_logic
);
END COMPONENT;
COMPONENT mercury_io
GENERIC
(
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output :string := "false";
output_register_mode : string := "none";
output_reset : string := "none";
output_power_up : string := "low";
oe_register_mode : string := "none";
oe_reset : string := "none";
oe_power_up : string := "low";
input_register_mode : string := "none";
input_reset : string := "none";
input_power_up : string := "low";
bus_hold : string := "false");
PORT
(
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
oeclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
padio : inout std_logic );
END COMPONENT;
COMPONENT mercury_hssi_synchronizer
GENERIC (
channel_width : integer := 20;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk0_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk0_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_we_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_we_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_re_clk1_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_re_clk1_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_we_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_we_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk1_dataout_posedge : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk0_overflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_areset_overflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_empty_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk1_empty_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_we : VitalDelayType01 := DefpropDelay01;
tipd_re : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefpropDelay01));
PORT (
clk0 : in std_logic;
clk1 : in std_logic;
datain : in std_logic_vector(19 downto 0);
we : in std_logic := '1';
re : in std_logic := '1';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
empty : out std_logic;
overflow : out std_logic;
dataout : out std_logic_vector(19 downto 0));
END COMPONENT;
END MERCURY_COMPONENTS;
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