mercury_atoms.vhd
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VHD
1,341 行
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
multsela : in std_logic := '1';
multselb : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
multout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic);
end mercury_lcell;
architecture vital_le_atom of mercury_lcell is
signal dffin : std_logic;
COMPONENT mercury_asynch_lcell
GENERIC (operation_mode : string := "normal";
output_mode : string := "comb_and_reg";
multiplier_output : string := "true";
multiplier_mux_source : string := "gnd";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_multsela_combout : VitalDelayType01 := DefPropDelay01;
tpd_multselb_combout : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_multsela_regin : VitalDelayType01 := DefPropDelay01;
tpd_multselb_regin : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_multout : VitalDelayType01 := DefPropDelay01;
tpd_datab_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_multout : VitalDelayType01 := DefPropDelay01;
tpd_multsela_multout : VitalDelayType01 := DefPropDelay01;
tpd_multselb_multout : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_multout : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_multout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_multdataa : VitalDelayType01 := DefPropDelay01;
tipd_multdatab : VitalDelayType01 := DefPropDelay01;
tipd_multsela : VitalDelayType01 := DefPropDelay01;
tipd_multselb : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
multsela : in std_logic := '1';
multselb : in std_logic := '1';
multdataa : in std_logic := '1';
multdatab : in std_logic := '1';
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic;
multout : out std_logic;
regin : out std_logic);
END COMPONENT;
COMPONENT mercury_lcell_register
GENERIC (
power_up : string := "low";
packed_mode : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_apre_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tperiod_clk_posedge : VitalDelayType := DefPulseWdthCnst;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_apre : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
PORT (clk : in std_logic := '0';
datain : in std_logic := '1';
datac : in std_logic := '1';
apre : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic);
END COMPONENT;
begin
lecomb: mercury_asynch_lcell
generic map (operation_mode => operation_mode, output_mode => output_mode,
lut_mask => lut_mask, cin_used => cin_used, cin0_used => cin0_used, cin1_used => cin1_used, multiplier_mux_source => multiplier_mux_source)
port map (dataa => dataa, datab => datab, datac => datac, datad => datad,
multsela => multsela, multselb => multselb,
multdataa => dataa, multdatab => datab,
cin => cin, cin0 => cin0, cin1 => cin1,
combout => combout, cout => cout, cout0 => cout0, cout1 => cout1, regin => dffin, multout => multout);
lereg: mercury_lcell_register
generic map (power_up => power_up, packed_mode => packed_mode)
port map (clk => clk, datain => dffin, datac => datac, apre => apre,
aclr => aclr, aload => aload, sclr => sclr, sload => sload, ena => ena,
devclrn => devclrn, devpor => devpor, regout => regout);
end vital_le_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : MERCURY_ASYNCH_MEM
--
-- Description : Timing simulation model for the asynchronous RAM array
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY ieee, mercury;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE mercury.atom_pack.all;
ENTITY mercury_asynch_mem is
GENERIC (
operation_mode : string := "single_port";
port_a_operation_mode : string := "single_port";
port_b_operation_mode : string := "single_port";
port_a_write_deep_ram_mode : string := "off";
port_a_write_address_width : integer := 1;
port_a_write_first_address : integer := 0;
port_a_write_last_address : integer := 4095;
port_a_write_data_width : integer := 1;
port_a_read_deep_ram_mode : string := "off";
port_a_read_address_width : integer := 1;
port_a_read_first_address : integer := 0;
port_a_read_last_address : integer := 4095;
port_a_read_data_width : integer := 1;
port_b_write_deep_ram_mode : string := "off";
port_b_write_address_width : integer := 1;
port_b_write_first_address : integer := 0;
port_b_write_last_address : integer := 4095;
port_b_write_data_width : integer := 1;
port_b_read_deep_ram_mode : string := "off";
port_b_read_address_width : integer := 1;
port_b_read_first_address : integer := 0;
port_b_read_last_address : integer := 4095;
port_b_read_data_width : integer := 1;
port_a_read_enable_clock : string := "none";
port_b_read_enable_clock : string := "none";
port_a_write_logic_clock : string := "none";
port_b_write_logic_clock : string := "none";
init_file : string := "none";
port_a_init_file : string := "none";
port_b_init_file : string := "none";
mem1 : std_logic_vector(512 downto 1);
mem2 : std_logic_vector(512 downto 1);
mem3 : std_logic_vector(512 downto 1);
mem4 : std_logic_vector(512 downto 1);
mem5 : std_logic_vector(512 downto 1);
mem6 : std_logic_vector(512 downto 1);
mem7 : std_logic_vector(512 downto 1);
mem8 : std_logic_vector(512 downto 1);
bit_number : integer := 0;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
-- timing check generics for PORT A
tsetup_portawaddr_portawe_noedge_posedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portawaddr_portawe_noedge_negedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_portadatain_portawe_noedge_negedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portadatain_portawe_noedge_negedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_portaraddr_portare_noedge_negedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_portaraddr_portare_noedge_negedge : VitalDelayArrayType(15 downto 0) := (OTHERS => DefSetupHoldCnst);
-- path delay generics for PORT A
tpd_portaraddr_portadataout : VitalDelayArrayType01(255 downto 0) := (OTHERS => DefPropDelay01);
-- tpd_portawaddr_portadataout : VitalDelayArrayType01(255 downto 0) := (OTHERS => DefPropDelay01);
tpd_portare_portadataout : VitalDelayArrayType01(15 downto 0) := (OTHERS => DefPropDelay01);
tpd_portadatain_portadataout : VitalDelayArrayType01(255 downto 0) := (OTHERS => DefPropDelay01);
tpd_portawe_portadataout : VitalDelayArrayType01(15 downto 0) := (OTHERS => DefPropDelay01);
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