mercury_atoms.vhd
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VHD
1,341 行
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Quartus II 3.0 Build 197 06/18/2003
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
package atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE apex20ke_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
TYPE mercury_mem_data IS ARRAY (0 to 63) of STD_LOGIC_VECTOR (31 downto 0);
end atom_pack;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
package body atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
end atom_pack;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for MERCURY Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, mercury;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE mercury.atom_pack.all;
ENTITY mercury_asynch_lcell is
GENERIC (operation_mode : string := "normal";
output_mode : string := "comb_and_reg";
multiplier_output : string := "true";
multiplier_mux_source : string := "gnd";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_multsela_combout : VitalDelayType01 := DefPropDelay01;
tpd_multselb_combout : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_multsela_regin : VitalDelayType01 := DefPropDelay01;
tpd_multselb_regin : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_multout : VitalDelayType01 := DefPropDelay01;
tpd_datab_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_multout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_multout : VitalDelayType01 := DefPropDelay01;
tpd_multsela_multout : VitalDelayType01 := DefPropDelay01;
tpd_multselb_multout : VitalDelayType01 := DefPropDelay01;
tpd_multdataa_multout : VitalDelayType01 := DefPropDelay01;
tpd_multdatab_multout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_multdataa : VitalDelayType01 := DefPropDelay01;
tipd_multdatab : VitalDelayType01 := DefPropDelay01;
tipd_multsela : VitalDelayType01 := DefPropDelay01;
tipd_multselb : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
multsela : in std_logic := '1';
multselb : in std_logic := '1';
multdataa : in std_logic := '1';
multdatab : in std_logic := '1';
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic;
multout : out std_logic;
regin : out std_logic);
attribute VITAL_LEVEL0 of mercury_asynch_lcell : ENTITY is TRUE;
end mercury_asynch_lcell;
architecture vital_le of mercury_asynch_lcell is
attribute VITAL_LEVEL0 of vital_le : architecture is TRUE;
signal dataa_ipd, datab_ipd : std_logic;
signal multdataa_ipd, multdatab_ipd : std_logic;
signal datac_ipd, datad_ipd : std_logic;
signal cin_ipd, cin0_ipd, cin1_ipd : std_logic;
signal multsela_ipd, multselb_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
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