apexii_atoms.vhd
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VHD
1,593 行
PORT(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
attribute VITAL_LEVEL0 of apexii_asynch_io : ENTITY is TRUE;
end apexii_asynch_io;
ARCHITECTURE behave of apexii_asynch_io is
attribute VITAL_LEVEL0 of behave : ARCHITECTURE is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_padio := prev_value;
tmp_combout := to_x01z(padio_ipd);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- APEXII_IO
--
LIBRARY IEEE, apexii;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use apexii.atom_pack.all;
LIBRARY apexii;
use apexii.all;
ENTITY apexii_io is
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output :string := "false";
output_register_mode : string := "none";
output_reset : string := "none";
output_power_up : string := "low";
oe_register_mode : string := "none";
oe_reset : string := "none";
oe_power_up : string := "low";
input_register_mode : string := "none";
input_reset : string := "none";
input_power_up : string := "low";
bus_hold : string := "false";
tie_off_output_clock_enable : string := "false";
tie_off_oe_clock_enable : string := "false";
extend_oe_disable : string := "false"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
padio : inout std_logic
);
end apexii_io;
ARCHITECTURE structure of apexii_io is
component apexii_asynch_io
GENERIC(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false");
PORT(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component DFFE
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end component;
component mux21
GENERIC(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
PORT ( A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
end component;
component and1
GENERIC(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
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