apexii_atoms.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 1,593 行 · 第 1/5 页
VHD
1,593 行
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cascin_ipd'last_event, tpd_cascin_regin, TRUE),
6 => (qfbkin'last_event, tpd_qfbkin_regin, TRUE)),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cascout,
OutSignalName => "CASCOUT",
OutTemp => tmp_cascout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cascout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cascout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cascout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cascout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cascout, TRUE),
5 => (cascin_ipd'last_event, tpd_cascin_cascout, TRUE),
6 => (qfbkin'last_event, tpd_qfbkin_cascout, TRUE)),
GlitchData => cascout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
5 => (qfbkin'last_event, tpd_qfbkin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le;
LIBRARY IEEE, apexii;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use apexii.atom_pack.all;
ENTITY apexii_lcell_register is
GENERIC (
power_up : string := "low";
packed_mode : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tperiod_clk_posedge : VitalDelayType := DefPulseWdthCnst;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
PORT (clk :in std_logic;
datain : in std_logic := '1';
datac : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic;
qfbko : out std_logic);
attribute VITAL_LEVEL0 of apexii_lcell_register : ENTITY is TRUE;
end apexii_lcell_register;
ARCHITECTURE vital_le_reg of apexii_lcell_register is
attribute VITAL_LEVEL0 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd, sload_ipd, datac_ipd : std_logic;
signal clk_ipd, aclr_ipd, sclr_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, devclrn, devpor, sclr_ipd, ena_ipd, datain, datac_ipd, sload_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable PeriodData_clk : VitalPeriodDataType := VitalPeriodDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbko_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata, setbit : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_qfbko : std_logic;
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_clk,
PeriodData => PeriodData_clk,
TestSignal => clk_ipd,
TestSignalName => "CLK",
Period => tperiod_clk_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (aclr_ipd = '1') then
iregout := '0';
elsif (violation = 'X') then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := datac_ipd;
else
if packed_mode = "true" then
iregout := datac_ipd;
else
iregout := datain;
end if;
end if;
end if;
end if;
tmp_regout := iregout;
tmp_qfbko := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => qfbko_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbko,
OutSignalName => "QFBKO",
OutTemp => tmp_qfbko,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbko_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_qfbko_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?