flex10ke_atoms.vhd
来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 1,471 行 · 第 1/5 页
VHD
1,471 行
end if;
if (open_drain_output = "false") then
tmp_padio := temp;
elsif (open_drain_output = "true") then
if ((reg_source_mode = "data_in_to_pin") and (feedback_mode /= "from_pin")) then
if (temp = '0') then
tmp_padio := '0';
else
tmp_padio := 'Z';
end if;
else
if (datain_ipd = '1') then
tmp_padio := 'Z';
else
tmp_padio := '0';
end if;
end if;
end if;
elsif ((operation_mode = "bidir") and (oe_ipd = '1')) then
if (open_drain_output = "false") then
tmp_padio := tri_in;
elsif (open_drain_output = "true") then
if (tri_in = '0') then
tmp_padio := '0';
else
tmp_padio := 'Z';
end if;
end if;
else
tmp_padio := 'Z';
end if;
----------------------
-- Path Delay Section
----------------------
if (feedback_mode ="from_pin") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => tmp_dataout,
Paths => ( 0 => (padio_ipd'last_event,
tpd_padio_dataout,
TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dffeQ,
Paths => ( 0 => (dffeQ'last_event,
tpd_dffeQ_dataout,
TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "PADIO",
OutTemp => tmp_padio,
Paths => (0 => (dffeQ'last_event,
tpd_dffeQ_padio,
TRUE),
1 => (oe_ipd'last_event,
tpd_oe_padio_posedge,
oe_ipd = '1'),
2 => (oe_ipd'last_event,
tpd_oe_padio_negedge,
oe_ipd = '0'),
3 => (datain_ipd'last_event,
tpd_datain_padio,
(reg_source_mode = "none" or reg_source_mode = "data_in"
or reg_source_mode = "pin_only"))),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dffeD,
OutSignalName => "DFFED",
OutTemp => reg_indata,
Paths => (0 => (datain_ipd'last_event, (0 ns, 0 ns),
reg_source_mode = "data_in" or
reg_source_mode = "data_in_to_pin"),
1 => (padio_ipd'last_event, (0 ns, 0 ns),
reg_source_mode = "pin_only" or
reg_source_mode = "pin_loop")),
GlitchData => dffeD_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_asynch_io;
LIBRARY IEEE, flex10ke;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE flex10ke.atom_pack.all;
ENTITY flex10ke_io is
GENERIC (operation_mode : string := "input";
reg_source_mode : string := "none";
feedback_mode : string := "from_pin";
power_up : string := "low";
open_drain_output : string := "false");
PORT (clk : in std_logic := '0';
datain : in std_logic := '1';
aclr : in std_logic := '0';
ena : in std_logic := '1';
oe : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
dataout : out std_logic);
end flex10ke_io;
ARCHITECTURE arch of flex10ke_io is
signal reg_clr, reg_pre : std_logic := '1';
signal ioreg_clr : std_logic := '1';
signal vcc : std_logic := '1';
signal dffeD : std_logic;
signal data_out : std_logic;
signal dffe_Q : std_logic;
COMPONENT DFFE_IO
GENERIC(
TimingChecksOn: Boolean := true;
XGenerationOn: Boolean := false;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
COMPONENT flex10ke_asynch_io
GENERIC (operation_mode : string := "input";
reg_source_mode : string := "none";
feedback_mode : string := "from_pin";
open_drain_output : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_padio_dataout : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_dffeQ_padio : VitalDelayType01 := DefPropDelay01;
tpd_dffeQ_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01);
PORT (datain : in std_logic;
dffeQ : in std_logic;
oe : in std_logic;
padio : inout std_logic;
dffeD : out std_logic;
dataout : out std_logic);
end COMPONENT;
begin
reg_clr <= devpor when power_up = "low" else vcc;
ioreg_clr <= devclrn and (not aclr) and reg_clr;
inst1: flex10ke_asynch_io
generic map (operation_mode => operation_mode,
reg_source_mode => reg_source_mode,
feedback_mode => feedback_mode,
open_drain_output => open_drain_output)
port map (datain => datain, oe => oe, padio => padio,
dffeD => dffeD, dffeQ => dffe_Q,
dataout => data_out);
io_reg: dffe_io
port map (D => dffeD, clk => clk, ena => ena, Q => dffe_Q,
CLRN => ioreg_clr);
dataout <= data_out;
end arch;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : FLEX10KE_ASYNCH_MEM
--
-- Description : Timing simulation model for the asynchronous RAM array.
-- Size of array : 2048x1
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, flex10ke;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE flex10ke.atom_pack.all;
ENTITY flex10ke_asynch_mem IS
GENERIC (
logical_ram_depth : integer := 2048;
inifile : string := "none";
address_width : integer := 1;
first_address : integer := 0;
last_address : integer := 2047;
mem1 : std_logic_vector(512 downto 1) ;
mem2 : std_logic_vector(512 downto 1) ;
mem3 : std_logic_vector(512 downto 1) ;
mem4 : std_logic_vector(512 downto 1) ;
bit_number : integer := 0;
write_logic_clock : string := "none";
read_enable_clock : string := "none";
data_out_clock : string := "none";
operation_mode : string := "single_port";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_waddr_we_noedge_posedge : VitalDelayArrayType(10 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_waddr_we_noedge_negedge : VitalDelayArrayType(10 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_we_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_we_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_raddr_re_noedge_negedge : VitalDelayArrayType(10 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_raddr_re_noedge_negedge : VitalDelayArrayType(10 downto 0) := (OTHERS => DefSetupHoldCnst);
tpd_raddr_dataout : VitalDelayArrayType01(10 downto 0) := (OTHERS => DefPropDelay01);
tpd_waddr_dataout : VitalDelayArrayType01(10 downto 0) := (OTHERS => DefPropDelay01);
tpd_re_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_we_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_we : VitalDelayType01 := DefPropDelay01;
tipd_re : VitalDelayType01 := DefPropDelay01;
tipd_raddr : VitalDelayArrayType01(10 downto 0) := (OTHERS => DefPropDelay01);
tipd_waddr : VitalDelayArrayType01(10 downto 0) := (OTHERS => DefPropDelay01);
tpw_we_posedge : VitalDelayType := 0 ns;
tpw_re_posedge : VitalDelayType := 0 ns
);
PORT (datain : in std_logic := '0';
we : in std_logic := '0';
re : in std_logic := '1';
raddr : in std_logic_vector(10 downto 0) := "00000000000";
waddr : in std_logic_vector(10 downto 0) := "00000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
modesel : in std_logic_vector(15 downto 0) := "0000000000000000";
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