flex10ke_atoms.vhd

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  PORT (clk     : in std_logic := '0';
        dataa     : in std_logic := '1';
        datab     : in std_logic := '1';
        datac     : in std_logic := '1';
        datad     : in std_logic := '1';
        aclr    : in std_logic := '0';
        aload : in std_logic := '0';
        cin   : in std_logic := '0';
        cascin     : in std_logic := '1';
        devclrn   : in std_logic := '1';
        devpor    : in std_logic := '1';
        combout   : out std_logic;
        regout    : out std_logic;
        cout  : out std_logic;
        cascout    : out std_logic);
end flex10ke_lcell;
        
ARCHITECTURE vital_le_atom of flex10ke_lcell is

signal dffin : std_logic;
signal qfbk  : std_logic;

COMPONENT flex10ke_asynch_lcell 
  GENERIC (operation_mode    : string := "normal";
      output_mode   : string := "comb_and_reg";
      lut_mask       : string := "ffff";
      cin_used       : string := "false";
      TimingChecksOn: Boolean := True;
      MsgOn: Boolean := DefGlitchMsgOn;
      XOn: Boolean := DefGlitchXOn;
      MsgOnChecks: Boolean := DefMsgOnChecks;
      XOnChecks: Boolean := DefXOnChecks;
      InstancePath: STRING := "*";
      tpd_dataa_combout                 : VitalDelayType01 := DefPropDelay01;
      tpd_datab_combout                 : VitalDelayType01 := DefPropDelay01;
      tpd_datac_combout                 : VitalDelayType01 := DefPropDelay01;
      tpd_datad_combout                 : VitalDelayType01 := DefPropDelay01;
      tpd_qfbkin_combout                : VitalDelayType01 := DefPropDelay01;
      tpd_cin_combout                   : VitalDelayType01 := DefPropDelay01;
      tpd_cascin_combout                : VitalDelayType01 := DefPropDelay01;
      tpd_dataa_regin                   : VitalDelayType01 := DefPropDelay01;
      tpd_datab_regin                   : VitalDelayType01 := DefPropDelay01;
      tpd_datac_regin                   : VitalDelayType01 := DefPropDelay01;
      tpd_datad_regin                   : VitalDelayType01 := DefPropDelay01;
      tpd_qfbkin_regin                  : VitalDelayType01 := DefPropDelay01;
      tpd_cin_regin                     : VitalDelayType01 := DefPropDelay01;
      tpd_cascin_regin                  : VitalDelayType01 := DefPropDelay01;
      tpd_dataa_cout                        : VitalDelayType01 := DefPropDelay01;
      tpd_datab_cout                        : VitalDelayType01 := DefPropDelay01;
      tpd_datac_cout                    : VitalDelayType01 := DefPropDelay01;
      tpd_datad_cout                    : VitalDelayType01 := DefPropDelay01;
      tpd_qfbkin_cout                   : VitalDelayType01 := DefPropDelay01;
      tpd_cin_cout                        : VitalDelayType01 := DefPropDelay01;
      tpd_cascin_cascout                : VitalDelayType01 := DefPropDelay01;
      tpd_cin_cascout                    : VitalDelayType01 := DefPropDelay01;
      tpd_dataa_cascout                        : VitalDelayType01 := DefPropDelay01;
      tpd_datab_cascout                        : VitalDelayType01 := DefPropDelay01;
      tpd_datac_cascout                    : VitalDelayType01 := DefPropDelay01;
      tpd_datad_cascout                    : VitalDelayType01 := DefPropDelay01;
      tpd_qfbkin_cascout                : VitalDelayType01 := DefPropDelay01;
      tipd_dataa                        : VitalDelayType01 := DefPropDelay01; 
      tipd_datab                        : VitalDelayType01 := DefPropDelay01; 
      tipd_datac                        : VitalDelayType01 := DefPropDelay01; 
      tipd_datad                        : VitalDelayType01 := DefPropDelay01; 
      tipd_cin                          : VitalDelayType01 := DefPropDelay01; 
      tipd_cascin                        : VitalDelayType01 := DefPropDelay01); 

  PORT (
        dataa     : in std_logic := '1';
        datab     : in std_logic := '1';
        datac     : in std_logic := '1';
        datad     : in std_logic := '1';
        cin       : in std_logic := '0';
        cascin    : in std_logic := '1';
        qfbkin    : in std_logic := '0';
        combout   : out std_logic;
        cout      : out std_logic;
        cascout   : out std_logic;
        regin     : out std_logic);
end COMPONENT;

COMPONENT flex10ke_lcell_register
  GENERIC (operation_mode : string := "normal";
      clock_enable_mode : string := "false";
      packed_mode   : string := "false";
      TimingChecksOn: Boolean := True;
      MsgOn: Boolean := DefGlitchMsgOn;
      XOn: Boolean := DefGlitchXOn;
      MsgOnChecks: Boolean := DefMsgOnChecks;
      XOnChecks: Boolean := DefXOnChecks;
      InstancePath: STRING := "*";
      tsetup_datain_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tsetup_dataa_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tsetup_datab_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tsetup_datac_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tsetup_datad_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tsetup_aload_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_datain_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_dataa_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_datab_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_datac_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_datad_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      thold_aload_clk_noedge_posedge        : VitalDelayType := DefSetupHoldCnst;
      tpd_clk_regout_posedge                : VitalDelayType01 := DefPropDelay01;
      tpd_aclr_regout_posedge                : VitalDelayType01 := DefPropDelay01;
      tpd_clk_qfbko_posedge                : VitalDelayType01 := DefPropDelay01;
      tpd_aclr_qfbko_posedge                : VitalDelayType01 := DefPropDelay01;
      tperiod_clk_posedge               : VitalDelayType := DefPulseWdthCnst;
      tipd_dataa                          : VitalDelayType01 := DefPropDelay01; 
      tipd_datab                          : VitalDelayType01 := DefPropDelay01; 
      tipd_datac                          : VitalDelayType01 := DefPropDelay01; 
      tipd_datad                          : VitalDelayType01 := DefPropDelay01; 
      tipd_aclr                         : VitalDelayType01 := DefPropDelay01; 
      tipd_clk                          : VitalDelayType01 := DefPropDelay01;
      tipd_aload                         : VitalDelayType01 := DefPropDelay01); 
  PORT (clk     : in std_logic;
        datain     : in std_logic := '1';
        dataa     : in std_logic := '1';
        datab     : in std_logic := '1';
        datac     : in std_logic := '1';
        datad     : in std_logic := '1';
        aclr    : in std_logic := '0';
        aload : in std_logic := '0';
        devclrn   : in std_logic := '1';
        devpor    : in std_logic := '1';
        regout    : out std_logic;
        qfbko     : out std_logic);
end COMPONENT;

begin

lecomb: flex10ke_asynch_lcell
        generic map (operation_mode => operation_mode, output_mode => output_mode,
                     lut_mask => lut_mask, cin_used => cin_used)
        port map (dataa => dataa, datab => datab, datac => datac, datad => datad,
                  cin => cin, cascin => cascin, qfbkin => qfbk,
                  combout => combout, cout => cout, cascout => cascout, regin => dffin);

lereg: flex10ke_lcell_register
        generic map (operation_mode => operation_mode, clock_enable_mode => clock_enable_mode, packed_mode => packed_mode)
          port map (clk => clk, datain => dffin, dataa => dataa, datab => datab, datac => datac, datad => datad, 
                aclr => aclr, aload => aload, devclrn => devclrn, devpor => devpor, regout => regout, qfbko => qfbk);


end vital_le_atom;

--
--
--  FLEX10KE_IO Model
--
--
LIBRARY IEEE, flex10ke;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE flex10ke.atom_pack.all;

ENTITY flex10ke_asynch_io is
   GENERIC (operation_mode : string := "input";
      reg_source_mode :  string := "none";
      feedback_mode : string := "from_pin";
      open_drain_output : string := "false";
      TimingChecksOn: Boolean := True;
      MsgOn: Boolean := DefGlitchMsgOn;
      XOn: Boolean := DefGlitchXOn;
      MsgOnChecks: Boolean := DefMsgOnChecks;
      XOnChecks: Boolean := DefXOnChecks;
      InstancePath: STRING := "*";

      tpd_datain_padio                         : VitalDelayType01 := DefPropDelay01;
      tpd_padio_dataout                  : VitalDelayType01 := DefPropDelay01;
      tpd_oe_padio_posedge               : VitalDelayType01 := DefPropDelay01;
      tpd_oe_padio_negedge               : VitalDelayType01 := DefPropDelay01;
      tpd_dffeQ_padio                         : VitalDelayType01 := DefPropDelay01;
      tpd_dffeQ_dataout                         : VitalDelayType01 := DefPropDelay01;

      tipd_datain                        : VitalDelayType01 := DefPropDelay01;
      tipd_oe                            : VitalDelayType01 := DefPropDelay01;
      tipd_padio                         : VitalDelayType01 := DefPropDelay01);

    PORT (datain: in std_logic;
          dffeQ : in std_logic;
          oe           : in std_logic;
          padio : inout std_logic;
          dffeD : out std_logic;
          dataout : out std_logic);

    attribute VITAL_LEVEL0 of flex10ke_asynch_io : ENTITY is TRUE;
end flex10ke_asynch_io;

ARCHITECTURE vital_asynch_io of flex10ke_asynch_io is
   attribute VITAL_LEVEL0 of vital_asynch_io : ARCHITECTURE is TRUE;

   signal oe_ipd : std_logic;
   signal datain_ipd, padio_ipd : std_logic;

begin
   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
      VitalWireDelay (datain_ipd, datain, tipd_datain);
      VitalWireDelay (padio_ipd, padio, tipd_padio);
      VitalWireDelay (oe_ipd, oe, tipd_oe);
   end block;

VITALtiming : process(datain_ipd, oe_ipd, padio_ipd, dffeQ)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_padio_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_padio_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable dffeD_VitalGlitchData : VitalGlitchDataType;

variable tri_in : std_logic := '0';
variable tmp_dataout, tmp_padio, oe_val, temp : std_logic;
variable reg_indata : std_logic := '0';
begin

        if ((reg_source_mode = "none") and
                     (feedback_mode = "none")) then
                if ((operation_mode = "output") or
                          (operation_mode = "bidir")) then
                     tri_in := datain_ipd;
                end if;
        elsif ((reg_source_mode = "none") and
                     (feedback_mode = "from_pin")) then
                if (operation_mode = "input") then
                        tmp_dataout := to_x01z(padio_ipd);
                elsif (operation_mode = "bidir") then
                        tmp_dataout := to_x01z(padio_ipd);
                        tri_in := datain_ipd;
                end if;
        elsif ((reg_source_mode = "data_in") and
                        (feedback_mode = "from_reg")) then
                if ((operation_mode = "output") or
                          (operation_mode = "bidir")) then
                     tri_in := datain_ipd;        
                     reg_indata := datain_ipd;
                end if;
        elsif ((reg_source_mode = "pin_only") and
                        (feedback_mode = "from_reg"))   then
                if (operation_mode = "input") then
                        reg_indata := to_x01z(padio_ipd);
                elsif (operation_mode = "bidir")  then
                        tri_in := datain_ipd;
                        reg_indata := to_x01z(padio_ipd);
                end if;
        elsif ((reg_source_mode = "data_in_to_pin") and
                        (feedback_mode = "from_pin")) then
                if (operation_mode = "bidir") then
                        reg_indata := datain_ipd;
                        tri_in := dffeQ;
                        tmp_dataout := to_x01z(padio_ipd);
                end if;
        elsif ((reg_source_mode = "data_in_to_pin") and
                        (feedback_mode = "from_reg"))     then
                if ((operation_mode = "output") or
                          (operation_mode = "bidir")) then
                        reg_indata := datain_ipd;
                        tri_in := dffeQ;
                end  if;
        elsif ((reg_source_mode = "data_in_to_pin") and
                        (feedback_mode = "none"))       then
                if ((operation_mode = "output") or
                          (operation_mode = "bidir")) then
                        tri_in := dffeQ;
                        reg_indata := datain_ipd;
                end   if;
        elsif ((reg_source_mode = "pin_loop") and
                        (feedback_mode = "from_pin")) then
                if (operation_mode = "bidir") then
                        tri_in := dffeQ;
                        reg_indata := to_x01z(padio_ipd);
                        tmp_dataout := to_x01z(padio_ipd);
                end if;
        elsif ((reg_source_mode = "pin_loop") and
                        (feedback_mode = "from_reg")) then
                if (operation_mode = "bidir") then
                        reg_indata := to_x01z(padio_ipd);
                        tri_in := dffeQ;
                end if;
        end if;

        if (operation_mode = "output") then
           oe_val := to_x01z(oe_ipd);
           if (oe_val = '0') then
               temp := 'Z';
           else
               temp := tri_in;