flex10ke_atoms.vhd
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VHD
1,471 行
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datab_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datad_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbko_posedge : VitalDelayType01 := DefPropDelay01;
tperiod_clk_posedge : VitalDelayType := DefPulseWdthCnst;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
PORT (clk :in std_logic;
datain : in std_logic := '1';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic;
qfbko : out std_logic);
attribute VITAL_LEVEL0 of flex10ke_lcell_register : ENTITY is TRUE;
end flex10ke_lcell_register;
ARCHITECTURE vital_le_reg of flex10ke_lcell_register is
attribute VITAL_LEVEL0 of vital_le_reg : ARCHITECTURE is TRUE;
signal aload_ipd, dataa_ipd, datab_ipd, datac_ipd, datad_ipd : std_logic;
signal ena_ipd : std_logic := '1';
signal clk_ipd, aclr_ipd: std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, devclrn, devpor, ena_ipd, datain, dataa_ipd, datab_ipd, datac_ipd, datad_ipd, aload_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_dataa_clk : std_ulogic := '0';
variable Tviol_datab_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_datad_clk : std_ulogic := '0';
variable Tviol_aload_clk : std_ulogic := '0';
variable Tviol_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datab_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datad_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_aload_clk : VitalTimingDataType := VitalTimingDataInit;
variable PeriodData_clk : VitalPeriodDataType := VitalPeriodDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbko_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable inreg, temp: std_logic;
variable idata, setbit : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_qfbko : std_logic;
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT dataa_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT dataa_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa_ipd,
TestSignalName => "DATAA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge,
SetupLow => tsetup_dataa_clk_noedge_posedge,
HoldHigh => thold_dataa_clk_noedge_posedge,
HoldLow => thold_dataa_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datab_clk,
TimingData => TimingData_datab_clk,
TestSignal => datab_ipd,
TestSignalName => "DATAB",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datab_clk_noedge_posedge,
SetupLow => tsetup_datab_clk_noedge_posedge,
HoldHigh => thold_datab_clk_noedge_posedge,
HoldLow => thold_datab_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datad_clk,
TimingData => TimingData_datad_clk,
TestSignal => datad_ipd,
TestSignalName => "DATAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datad_clk_noedge_posedge,
SetupLow => tsetup_datad_clk_noedge_posedge,
HoldHigh => thold_datad_clk_noedge_posedge,
HoldLow => thold_datad_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT dataa_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_aload_clk,
TimingData => TimingData_aload_clk,
TestSignal => aload_ipd,
TestSignalName => "ALOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_aload_clk_noedge_posedge,
SetupLow => tsetup_aload_clk_noedge_posedge,
HoldHigh => thold_aload_clk_noedge_posedge,
HoldLow => thold_aload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_clk,
PeriodData => PeriodData_clk,
TestSignal => clk_ipd,
TestSignalName => "CLK",
Period => tperiod_clk_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT devpor) OR (NOT devclrn)) /= '1',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_dataa_clk or Tviol_datab_clk or Tviol_datac_clk or Tviol_datad_clk or
Tviol_aload_clk or Tviol_clk;
if clock_enable_mode = "true" then
ena_ipd <= dataa_ipd;
end if;
if (devclrn = '0') then
iregout := '0';
elsif (aclr_ipd = '1') then
iregout := '0';
elsif (violation = 'X') then
iregout := 'X';
elsif (aload = '1') then
iregout := datac_ipd;
elsif clk_ipd'event and clk_ipd = '1' then
if (ena_ipd = '1') then
if (operation_mode = "clrb_cntr") then
if (datab_ipd = '0') then
iregout := '0';
elsif (datad_ipd = '0') then
iregout := datac_ipd;
else
iregout := datain;
end if;
elsif (operation_mode = "up_dn_cntr") then
if (datad_ipd = '0') then
iregout := datac_ipd;
else
iregout := datain;
end if;
else
if (packed_mode = "true") then
iregout := datad_ipd;
else
iregout := datain;
end if;
end if;
end if;
end if;
tmp_regout := iregout;
tmp_qfbko := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => qfbko_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbko,
OutSignalName => "QFBKO",
OutTemp => tmp_qfbko,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbko_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_qfbko_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
LIBRARY IEEE, flex10ke;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE flex10ke.atom_pack.all;
ENTITY flex10ke_lcell is
GENERIC (operation_mode : string := "normal";
output_mode : string := "comb_and_reg";
clock_enable_mode : string := "false";
packed_mode : string := "false";
lut_mask : string := "ffff";
cin_used : string := "false");
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