📄 altera_mf_components.vhd
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end component;
component altaccumulate
generic (
width_in : integer:=4;
width_out : integer:=8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:=0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate"
);
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0'
);
end component;
component altsyncram
GENERIC (
operation_mode : string := "SINGLE_PORT"; -- "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 8; -- 1;
widthad_a : integer := 2; -- 1;
numwords_a : integer := 4; -- 1;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "CLEAR0";
wrcontrol_aclr_a : string := "CLEAR0";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 8; -- 1;
widthad_b : integer := 4; -- 1;
numwords_b : integer := 4; -- 1;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- width of a byte for byte enables
-- global parameters
byte_size : integer := 8;
-- SPR 106776 : remove redundant parameters
-- read_during_write_mode_port_a : string := "NEW_DATA_ON_FALLING_EDGE";
-- read_during_write_mode_port_b : string := "NEW_DATA_ON_FALLING_EDGE";
-- mixed-port feed-through mode choices are "OLD_DATA" or "DONT_CARE"
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
-- bogus lpm_hint parameter?
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
PORT (
wren_a : IN std_logic := '0';
wren_b : IN std_logic := '0';
rden_b : IN std_logic := '1';
data_a : IN std_logic_vector(width_a - 1 DOWNTO 0):= (others => '0');
data_b : IN std_logic_vector(width_b - 1 DOWNTO 0):= (others => '0');
address_a : IN std_logic_vector(widthad_a - 1 DOWNTO 0) := (others => '0');
address_b : IN std_logic_vector(widthad_b - 1 DOWNTO 0) := (others => '0');
-- two clocks only
clock0 : IN std_logic := '1';
clock1 : IN std_logic := '1';
clocken0 : IN std_logic := '1';
clocken1 : IN std_logic := '1';
aclr0 : IN std_logic := '0';
aclr1 : IN std_logic := '0';
byteena_a : IN std_logic_vector( (width_byteena_a - 1) downTO 0) := (others => 'Z');
byteena_b : IN std_logic_vector( (width_byteena_b - 1) downTO 0) := (others => 'Z');
q_a : OUT std_logic_vector(width_a - 1 DOWNTO 0);
q_b : OUT std_logic_vector(width_b - 1 DOWNTO 0));
END component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : positive; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 5;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk5_multiply_by : positive := 1;
clk4_multiply_by : positive := 1;
clk3_multiply_by : positive := 1;
clk2_multiply_by : positive := 1;
clk1_multiply_by : positive := 1;
clk0_multiply_by : positive := 1;
clk5_divide_by : positive := 1;
clk4_divide_by : positive := 1;
clk3_divide_by : positive := 1;
clk2_divide_by : positive := 1;
clk1_divide_by : positive := 1;
clk0_divide_by : positive := 1;
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
-- external clock specifications
extclk3_multiply_by : positive := 1;
extclk2_multiply_by : positive := 1;
extclk1_multiply_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk3_divide_by : positive := 1;
extclk2_divide_by : positive := 1;
extclk1_divide_by : positive := 1;
extclk0_divide_by : positive := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natur⌨️ 快捷键说明
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