_primary.vhd

来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity altgxb_parity_4b is
    port(
        data_in         : in     vl_logic_vector(3 downto 0);
        k28_6b_even     : in     vl_logic;
        k28_6b_odd      : in     vl_logic;
        k_6b            : in     vl_logic;
        s_6b            : in     vl_logic;
        ib_invalid_code : in     vl_logic_vector(1 downto 0);
        other_k_6b_even : in     vl_logic;
        other_k_6b_odd  : in     vl_logic;
        parity_6b_int   : in     vl_logic;
        invalid_6b_code : in     vl_logic;
        parity_4b_odd   : out    vl_logic;
        parity_4b_even  : out    vl_logic;
        parity_4b_even_3: out    vl_logic;
        parity_4b_odd_c : out    vl_logic;
        kchar_d         : out    vl_logic;
        parity_4b_out   : out    vl_logic;
        code_valid      : out    vl_logic
    );
end altgxb_parity_4b;