📄 cyclone_atoms.v
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parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
input clk, ena, aclr, aload, sclr, sload;
input datain, datac, regcascin;
input devclrn, devpor ;
output regout, qfbkout;
reg iregout;
wire reset;
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (x_on_violation == "on")
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload or negedge devclrn
or negedge devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout = 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
else if (devclrn == 'b0)
iregout = 'b0;
else if (iaclr === 'b1)
iregout = 'b0 ;
else if (iaload === 'b1)
iregout = idatac;
else if (iena === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (synch_mode == "on" )
begin
if (isclr === 'b1)
iregout = 'b0 ;
else if (isload === 'b1)
iregout = idatac;
else if (register_cascade_mode == "on")
iregout = iregcascin;
else
iregout = idatain;
end
else if (register_cascade_mode == "on")
iregout = iregcascin;
else
iregout = idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 'b1);
and (qfbkout, iregout, 'b1);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONE_LCELL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell (clk, dataa, datab, datac, datad, aclr, aload,
sclr, sload, ena, cin, cin0, cin1,
inverta, regcascin,
devclrn, devpor,
combout, regout, cout, cout0, cout1) ;
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "comb_only";
parameter lpm_type = "cyclone_lcell";
parameter x_on_violation = "on";
input dataa, datab, datac, datad;
input clk, aclr, aload, sclr, sload, ena;
input cin, cin0, cin1, inverta, regcascin;
input devclrn, devpor ;
output cout, cout0, cout1, regout, combout;
wire dffin, qfbkin;
cyclone_asynch_lcell lecomb (.dataa(dataa), .datab(datab),
.datac(datac), .datad(datad),
.cin(cin), .cin0(cin0), .cin1(cin1),
.inverta(inverta), .qfbkin(qfbkin),
.regin(dffin), .combout(combout),
.cout(cout), .cout0(cout0), .cout1(cout1));
defparam lecomb.operation_mode = operation_mode;
defparam lecomb.sum_lutc_input = sum_lutc_input;
defparam lecomb.cin_used = cin_used;
defparam lecomb.cin0_used = cin0_used;
defparam lecomb.cin1_used = cin1_used;
defparam lecomb.lut_mask = lut_mask;
cyclone_lcell_register lereg (.clk(clk), .aclr(aclr), .aload(aload),
.sclr(sclr), .sload(sload), .ena(ena),
.datain(dffin),
.datac(datac), .regcascin(regcascin),
.devclrn(devclrn), .devpor(devpor),
.regout(regout), .qfbkout(qfbkin));
defparam lereg.synch_mode = synch_mode;
defparam lereg.register_cascade_mode = register_cascade_mode;
defparam lereg.power_up = power_up;
defparam lereg.x_on_violation = x_on_violation;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONE_RAM_REGISTER
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_ram_register
(
data,
clk,
aclr,
ena,
if_clk,
if_aclr,
if_ena,
devclrn,
devpor,
power_up,
dataout,
aclrout,
done
);
parameter data_width = 144;
parameter sclr = "true";
parameter preset = "false";
input [143:0] data;
input clk;
input aclr;
input ena;
input if_clk;
input if_aclr;
input if_ena;
input devclrn;
input devpor;
input power_up;
output [143:0] dataout;
output aclrout;
output done;
wire [143:0] data_ipd;
wire clk_ipd;
wire aclr_ipd;
wire ena_ipd;
wire [143:0] dataout_tmp;
wire [143:0] dataout_tbuf;
wire done_tbuf;
reg aclrout_reg;
reg done_reg;
reg done_delta;
reg [143:0] dataout_reg;
reg [143:0] dataout_sreg;
reg viol_notifier;
buf data_buf0 (data_ipd[0], data[0]);
buf data_buf1 (data_ipd[1], data[1]);
buf data_buf2 (data_ipd[2], data[2]);
buf data_buf3 (data_ipd[3], data[3]);
buf data_buf4 (data_ipd[4], data[4]);
buf data_buf5 (data_ipd[5], data[5]);
buf data_buf6 (data_ipd[6], data[6]);
buf data_buf7 (data_ipd[7], data[7]);
buf data_buf8 (data_ipd[8], data[8]);
buf data_buf9 (data_ipd[9], data[9]);
buf data_buf10 (data_ipd[10], data[10]);
buf data_buf11 (data_ipd[11], data[11]);
buf data_buf12 (data_ipd[12], data[12]);
buf data_buf13 (data_ipd[13], data[13]);
buf data_buf14 (data_ipd[14], data[14]);
buf data_buf15 (data_ipd[15], data[15]);
buf data_buf16 (data_ipd[16], data[16]);
buf data_buf17 (data_ipd[17], data[17]);
buf data_buf18 (data_ipd[18], data[18]);
buf data_buf19 (data_ipd[19], data[19]);
buf data_buf20 (data_ipd[20], data[20]);
buf data_buf21 (data_ipd[21], data[21]);
buf data_buf22 (data_ipd[22], data[22]);
buf data_buf23 (data_ipd[23], data[23]);
buf data_buf24 (data_ipd[24], data[24]);
buf data_buf25 (data_ipd[25], data[25]);
buf data_buf26 (data_ipd[26], data[26]);
buf data_buf27 (data_ipd[27], data[27]);
buf data_buf28 (data_ipd[28], data[28]);
buf data_buf29 (data_ipd[29], data[29]);
buf data_buf30 (data_ipd[30], data[30]);
buf data_buf31 (data_ipd[31], data[31]);
buf data_buf32 (data_ipd[32], data[32]);
buf data_buf33 (data_ipd[33], data[33]);
buf data_buf34 (data_ipd[34], data[34]);
buf data_buf35 (data_ipd[35], data[35]);
buf data_buf36 (data_ipd[36], data[36]);
buf data_buf37 (data_ipd[37], data[37]);
buf data_buf38 (data_ipd[38], data[38]);
buf data_buf39 (data_ipd[39], data[39]);
buf data_buf40 (data_ipd[40], data[40]);
buf data_buf41 (data_ipd[41], data[41]);
buf data_buf42 (data_ipd[42], data[42]);
buf data_buf43 (data_ipd[43], data[43]);
buf data_buf44 (data_ipd[44], data[44]);
buf data_buf45 (data_ipd[45], data[45]);
buf data_buf46 (data_ipd[46], data[46]);
buf data_buf47 (data_ipd[47], data[47]);
buf data_buf48 (data_ipd[48], data[48]);
buf data_buf49 (data_ipd[49], data[49]);
buf data_buf50 (data_ipd[50], data[50]);
buf data_buf51 (data_ipd[51], data[51]);
buf data_buf52 (data_ipd[52], data[52]);
buf data_buf53 (data_ipd[53], data[53]);
buf data_buf54 (data_ipd[54], data[54]);
buf data_buf55 (data_ipd[55], data[55]);
buf data_buf56 (data_ipd[56], data[56]);
buf data_buf57 (data_ipd[57], data[57]);
buf data_buf58 (data_ipd[58], data[58]);
buf data_buf59 (data_ipd[59], data[59]);
buf data_buf60 (data_ipd[60], data[60]);
buf data_buf61 (data_ipd[61], data[61]);
buf data_buf62 (data_ipd[62], data[62]);
buf data_buf63 (data_ipd[63], data[63]);
buf data_buf64 (data_ipd[64], data[64]);
buf data_buf65 (data_ipd[65], data[65]);
buf data_buf66 (data_ipd[66], data[66]);
buf data_buf67 (data_ipd[67], data[67]);
buf data_buf68 (data_ipd[68], data[68]);
buf data_buf69 (data_ipd[69], data[69]);
buf data_buf70 (data_ipd[70], data[70]);
buf data_buf71 (data_ipd[71], data[71]);
buf data_buf72 (data_ipd[72], data[72]);
buf data_buf73 (data_ipd[73], data[73]);
buf data_buf74 (data_ipd[74], data[74]);
buf data_buf75 (data_ipd[75], data[75]);
buf data_buf76 (data_ipd[76], data[76]);
buf data_buf77 (data_ipd[77], data[77]);
buf data_buf78 (data_ipd[78], data[78]);
buf data_buf79 (data_ipd[79], data[79]);
buf data_buf80 (data_ipd[80], data[80]);
buf data_buf81 (data_ipd[81], data[81]);
buf data_buf82 (data_ipd[82], data[82]);
buf data_buf83 (data_ipd[83], data[83]);
buf data_buf84 (data_ipd[84], data[84]);
buf data_buf85 (data_ipd[85], data[85]);
buf data_buf86 (data_ipd[86], data[86]);
buf data_buf87 (data_ipd[87], data[87]);
buf data_buf88 (data_ipd[88], data[88]);
buf data_buf89 (data_ipd[89], data[89]);
buf data_buf90 (data_ipd[90], data[90]);
buf data_buf91 (data_ipd[91], data[91]);
buf data_buf92 (data_ipd[92], data[92]);
buf data_buf93 (data_ipd[93], data[93]);
buf data_buf94 (data_ipd[94], data[94]);
buf data_buf95 (data_ipd[95], data[95]);
buf data_buf96 (data_ipd[96], data[96]);
buf data_buf97 (data_ipd[97], data[97]);
buf data_buf98 (data_ipd[98], data[98]);
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