📄 stratix_atoms.v
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.devpor(devpor), .devclrn(devclrn));
defparam out_reg.async_reset = output_async_reset;
defparam out_reg.sync_reset = output_sync_reset;
defparam out_reg.power_up = output_power_up;
// out ddio reg
stratix_io_register out_ddio_reg (.regout(out_ddio_reg_out), .clk(outclk),
.ena(out_clk_ena), .datain(ddiodatain),
.areset(areset), .sreset(sreset),
.devpor(devpor), .devclrn(devclrn));
defparam out_ddio_reg.async_reset = output_async_reset;
defparam out_ddio_reg.sync_reset = output_sync_reset;
defparam out_ddio_reg.power_up = output_power_up;
// oe reg
stratix_io_register oe_reg (.regout (oe_reg_out), .clk(outclk),
.ena(oe_clk_ena), .datain(oe),
.areset(areset), .sreset(sreset),
.devpor(devpor), .devclrn(devclrn));
defparam oe_reg.async_reset = oe_async_reset;
defparam oe_reg.sync_reset = oe_sync_reset;
defparam oe_reg.power_up = oe_power_up;
// oe_pulse reg
stratix_io_register oe_pulse_reg (.regout(oe_pulse_reg_out), .clk(!outclk),
.ena(oe_clk_ena), .datain(oe_reg_out),
.areset(areset), .sreset(sreset),
.devpor(devpor), .devclrn(devclrn));
defparam oe_pulse_reg.async_reset = oe_async_reset;
defparam oe_pulse_reg.sync_reset = oe_sync_reset;
defparam oe_pulse_reg.power_up = oe_power_up;
assign oe_out = (oe_register_mode == "register") ?
(extend_oe_disable == "true" ? oe_pulse_reg_out && oe_reg_out : oe_reg_out) : oe;
and1 sel_delaybuf (.Y(outclk_delayed), .IN1(outclk));
mux21 ddio_data_mux (.MO (ddio_data),
.A (out_ddio_reg_out),
.B (out_reg_out),
.S (outclk_delayed)
);
assign tmp_datain = (ddio_mode == "output" || ddio_mode == "bidir") ?
ddio_data : ((operation_mode == "output" || operation_mode == "bidir") ?
((output_register_mode == "register") ? out_reg_out : datain) : 'b0);
// timing info in case output and/or input are not registered.
stratix_asynch_io inst1 (.datain(tmp_datain),
.oe(oe_out),
.regin(in_reg_out),
.ddioregin(in_ddio1_reg_out),
.padio(padio),
.delayctrlin(delayctrlin),
.combout(combout),
.regout(regout),
.ddioregout(ddioregout));
defparam inst1.operation_mode = operation_mode;
defparam inst1.bus_hold = bus_hold;
defparam inst1.open_drain_output = open_drain_output;
defparam inst1.phase_shift_delay = phase_shift_delay;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_MULT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_mult (dataa, datab, signa, signb, clk, aclr, ena,
dataout, scanouta, scanoutb, devclrn, devpor);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter output_clock = "none";
parameter dataa_clear = "none";
parameter datab_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter output_clear = "none";
parameter signa_internally_grounded = "false";
parameter signb_internally_grounded = "false";
parameter lpm_hint = "true";
parameter lpm_type = "stratix_mac_mult";
input [17:0] dataa;
input [17:0] datab;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
output [35:0] dataout;
output [17:0] scanouta;
output [17:0] scanoutb;
wire [35:0] mult_output;
wire [71:0] signa_out;
wire [71:0] signb_out;
wire [71:0] dataout_tmp;
wire [71:0] scanouta_tmp;
wire [71:0] scanoutb_tmp;
assign dataout = dataout_tmp[35:0];
stratix_mac_register dataa_mac_reg
(
.data ({{(54){1'b0}},dataa}),
.clk (clk[select_the(dataa_clock)]),
.aclr (aclr[select_the(dataa_clear)] || ~devclrn || ~devpor),
.ena (ena[select_the(dataa_clock)]),
.power_up(1'b0),
.dataout (scanouta_tmp),
.async ( ((dataa_clock == "none") ||
(dataa_clear == "none")) ? 1'b1 : 1'b0 )
);
defparam dataa_mac_reg.data_width = dataa_width;
stratix_mac_register datab_mac_reg
(
.data ({{(54){1'b0}},datab}),
.clk (clk[select_the(datab_clock)]),
.aclr (aclr[select_the(datab_clear)] || ~devclrn || ~devpor),
.ena (ena[select_the(datab_clock)]),
.power_up(1'b0),
.dataout (scanoutb_tmp),
.async ( ((datab_clock == "none") ||
(datab_clear == "none")) ? 1'b1 : 1'b0 )
);
defparam datab_mac_reg.data_width = datab_width;
stratix_mac_register signa_mac_reg
(
.data ({{(71){1'b0}},signa}),
.clk (clk[select_the(signa_clock)]),
.aclr (aclr[select_the(signa_clear)] || ~devclrn || ~devpor),
.ena (ena[select_the(signa_clock)]),
.power_up(1'b1),
.dataout (signa_out),
.async ( ((signa_clock == "none") ||
(signa_clear == "none")) ? 1'b1 : 1'b0 )
);
defparam signa_mac_reg.data_width = 1;
stratix_mac_register signb_mac_reg
(
.data ({{(71){1'b0}},signb}),
.clk (clk[select_the(signb_clock)]),
.aclr (aclr[select_the(signb_clear)] || ~devclrn || ~devpor),
.ena (ena[select_the(signb_clock)]),
.power_up(1'b1),
.dataout (signb_out),
.async ( ((signb_clock == "none") ||
(signb_clear == "none")) ? 1'b1 : 1'b0 )
);
defparam signb_mac_reg.data_width = 1;
stratix_mac_mult_internal mac_multiply
(
.dataa (scanouta_tmp[17:0]),
.datab (scanoutb_tmp[17:0]),
.signa ((signa_internally_grounded == "false") ? signa_out[0] : 1'b0),
.signb ((signb_internally_grounded == "false") ? signb_out[0] : 1'b0),
.scanouta(scanouta),
.scanoutb(scanoutb),
.dataout(mult_output)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = (dataa_width+datab_width);
stratix_mac_register dataout_mac_reg
(
.data ({{(36){1'b0}},mult_output}),
.clk (clk[select_the(output_clock)]),
.aclr (aclr[select_the(output_clear)] || ~devclrn || ~devpor),
.ena (ena[select_the(output_clock)]),
.power_up(1'b0),
.dataout (dataout_tmp),
.async ( ((output_clock == "none") ||
(output_clear == "none")) ? 1'b1 : 1'b0 )
);
defparam dataout_mac_reg.data_width = (dataa_width+datab_width);
//////////////////////////////////////////////////////////////////////////////
//
// SELECT_THE
//
//////////////////////////////////////////////////////////////////////////////
function integer select_the;
input [8*4:1] string_name;
begin
if (string_name == "0")
select_the = 0;
else if (string_name == "1")
select_the = 1;
else if (string_name == "2")
select_the = 2;
else if (string_name == "3")
select_the = 3;
else if (string_name == "none")
select_the = 0;
else
$display ("Error: select line must be a string");
end
endfunction
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_MULT_INTERNAL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_mult_internal (dataa, datab, signa, signb,
scanouta, scanoutb, dataout);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = 36;
input [17:0] dataa;
input [17:0] datab;
input signa;
input signb;
output [17:0] scanouta;
output [17:0] scanoutb;
output [35:0] dataout;
wire [35:0] dataout_tmp;
wire [dataa_width-1:0] abs_a;
wire [datab_width-1:0] abs_b;
wire [17:0] dataa_tmp;
wire [17:0] datab_tmp;
wire [17:0] scanouta_tmp;
wire [17:0] scanoutb_tmp;
wire [(dataa_width+datab_width)-1:0] abs_output;
wire neg;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(dataa => scanouta) = (0, 0);
(datab => scanoutb) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
buf dataa_buf0 (dataa_tmp[0], dataa[0]);
buf dataa_buf1 (dataa_tmp[1], dataa[1]);
buf dataa_buf2 (dataa_tmp[2], dataa[2]);
buf dataa_buf3 (dataa_tmp[3], dataa[3]);
buf dataa_buf4 (dataa_tmp[4], dataa[4]);
buf dataa_buf5 (dataa_tmp[5], dataa[5]);
buf dataa_buf6 (dataa_tmp[6], dataa[6]);
buf dataa_buf7 (dataa_tmp[7], dataa[7]);
buf dataa_buf8 (dataa_tmp[8], dataa[8]);
buf dataa_buf9 (dataa_tmp[9], dataa[9]);
buf dataa_buf10 (dataa_tmp[10], dataa[10]);
buf dataa_buf11 (dataa_tmp[11], dataa[11]);
buf dataa_buf12 (dataa_tmp[12], dataa[12]);
buf dataa_buf13 (dataa_tmp[13], dataa[13]);
buf dataa_buf14 (dataa_tmp[14], dataa[14]);
buf dataa_buf15 (dataa_tmp[15], dataa[15]);
buf dataa_buf16 (dataa_tmp[16], dataa[16]);
buf dataa_buf17 (dataa_tmp[17], dataa[17]);
buf datab_buf0 (datab_tmp[0], datab[0]);
buf datab_buf1 (datab_tmp[1], datab[1]);
buf datab_buf2 (datab_tmp[2], datab[2]);
buf datab_buf3 (datab_tmp[3], datab[3]);
buf datab_buf4 (datab_tmp[4], datab[4]);
buf datab_buf5 (datab_tmp[5], datab[5]);
buf datab_buf6 (datab_tmp[6], datab[6]);
buf datab_buf7 (datab_tmp[7], datab[7]);
buf datab_buf8 (datab_tmp[8], datab[8]);
buf datab_buf9 (datab_tmp[9], datab[9]);
buf datab_buf10 (datab_tmp[10], datab[10]);
buf datab_buf11 (datab_tmp[11], datab[11]);
buf datab_buf12 (datab_tmp[12], datab[12]);
buf datab_buf13 (datab_tmp[13], datab[13]);
buf datab_buf14 (datab_tmp[14], datab[14]);
buf datab_buf15 (datab_tmp[15], datab[15]);
buf datab_buf16 (datab_tmp[16], datab[16]);
buf datab_buf17 (datab_tmp[17], datab[17]);
assign abs_a = (signa && dataa_tmp[dataa_width-1]) ? (~dataa_tmp + 1) : dataa_tmp;
assign abs_b = (signb && datab_tmp[datab_width-1]) ? (~datab_tmp + 1) : datab_tmp;
assign scanouta_tmp = dataa_tmp;
assign scanoutb_tmp = datab_tmp;
assign neg = ((dataa_tmp[dataa_width-1] && signa) ^ (datab_tmp[datab_width-1] && signb));
assign abs_output = abs_a * abs_b;
assign dataout_tmp = neg ? (~abs_output + 1) : abs_output;
buf scanouta_buf0(scanouta[0], scanouta_tmp[0]);
buf scanouta_buf1(scanouta[1], scanouta_tmp[1]);
buf scanouta_buf2(scanouta[2], scanouta_tmp[2]);
buf scanouta_buf3(scanouta[3], scanouta_tmp[3]);
buf scanouta_buf4(scanouta[4], scanouta_tmp[4]);
buf scanouta_buf5(scanouta[5], scanouta_tmp[5]);
buf scanouta_buf6(scanouta[6], scanouta_tmp[6]);
buf scanouta_buf7(scanouta[7], scanouta_tmp[7]);
buf scanouta_buf8(scanouta[8], scanouta_tmp[8]);
buf scanouta_buf9(scanouta[9], scanouta_tmp[9]);
buf scanouta_buf10(scanouta[10], scanouta_tmp[10]);
buf scanouta_buf11(scanouta[11], scanouta_tmp[11]);
buf scanouta_buf12(scanouta[12], scanouta_tmp[12]);
buf scanouta_buf13(scanouta[13], scanouta_tmp[13]);
buf scanouta_buf14(scanouta[14], scanouta_tmp[14]);
buf scanouta_buf15(scanouta[15], scanouta_tmp[15]);
buf scanouta_buf16(scanouta[16], scanouta_tmp[16]);
buf scanouta_buf17(scanouta[17], scanouta_tmp[17]);
buf scanoutb_buf0(scanoutb[0], scanoutb_tmp[0]);
buf scanoutb_buf1(scanoutb[1], scanoutb_tmp[1]);
buf scanoutb_buf2(scanoutb[2], scanoutb_tmp[2]);
buf scanoutb_buf3(scanoutb[3], scanoutb_tmp[3]);
buf scanoutb_buf4(scanoutb[4], scanoutb_tmp[4]);
buf scanoutb_buf5(scanoutb[5], scanoutb_tmp[5]);
buf scanoutb_buf6(scanoutb[6], scanoutb_tmp[6]);
buf scanoutb_buf7(scanoutb[7], scanoutb_tmp[7]);
buf scanoutb_buf8(scanoutb[8], scanoutb_tmp[8]);
buf scanoutb_buf9(scanoutb[9], scanoutb_tmp[9]);
buf scanoutb_buf10(scanoutb[10], scanoutb_tmp[10]);
buf scanoutb_buf11(scanoutb[11], scanoutb_tmp[11]);
buf scanoutb_buf12(scanoutb[12], scanoutb_tmp[12]);
buf scanoutb_buf13(scanoutb[13], scanoutb_tmp[13]);
buf scanoutb_buf14(scanoutb[14], scanoutb_tmp[14]);
buf scanoutb_buf15(scanoutb[15], scanoutb_tmp[15]);
buf scanoutb_buf16(scanoutb[16], scanoutb_tmp[16]);
buf scanoutb_buf17(scanoutb[17], scanoutb_tmp[17]);
buf dataout_buf0(dataout[0], dataout_tmp[0]);
buf dataout_buf1(dataout[1], dataout_tmp[1]);
buf dataout_buf2(dataout[2], dataout_tmp[2]);
buf dataout_buf3(dataout[3], dataout_tmp[3]);
buf dataout_buf4(dataout[4], dataout_tmp[4]);
buf dataout_buf5(dataout[5], dataout_tmp[5]);
buf dataout_buf6(dataout[6], dataout_tmp[6]);
buf dataout_buf7(dataout[7], dataout_tmp[7]);
buf dataout_buf8(dataout[8], dataout_tmp[8]);
buf dataout_buf9(dataout[9], dataout_tmp[9]);
buf dataout_buf10(dataout[10], dataout_tmp[10]);
buf dataout_buf11(dataout[11], dataout_tmp[11]);
buf dataout_buf12(dataout[12], dataout_tmp[12]);
buf dataout_buf13(dataout[13], dataout_tmp[13]);
buf dataout_buf14(dataout[14], dataout_tmp[14]);
buf dataout_buf15(dataout[15], dataout_tmp[15]);
buf dataout_buf16(dataout[16], dataout_tmp[16]);
buf dataout_buf17(dataout[17], dataout_tmp[17]);
buf dataout_buf18(dataout[18], dataout_tmp[18]);
buf dataout_buf19(dataout[19], dataout_tmp[19]);
buf dataout_buf20(dataout[20], dataout_tmp[20]);
buf dataout_buf21(dataout[21], dataout_tmp[21]);
buf dataout_buf22(dataout[22], dataout_tmp[22]);
buf dataout_buf23(dataout[23], dataout_tmp[23]);
buf dataout_buf24(dataout[24], dataout_tmp[24]);
buf dataout_buf25(dataout[25], dataout_tmp[25]);
buf dataout_buf26(dataout[26], dataout_tmp[26]);
buf dataout_buf27(dataout[27], dataout_tmp[27]);
buf dataout_buf28(dataout[28], dataout_tmp[28]);
buf dataout_buf29(dataout[29], dataout_tmp[29]);
buf dataout_buf30(dataout[30], dataout_tmp[30]);
buf dataout_buf31(dataout[31], dataout_tmp[31]);
buf dataout_buf32(dataout[32], dataout_tmp[32]);
buf dataout_buf33(dataout[33], dataout_tmp[33]);
buf dataout_buf34(dataout[34], dataout_tmp[34]);
buf dataout_buf35(dataout[35], dataout_tmp[35]);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_OUT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_out (dataa, datab, datac, datad, zeroacc,
addnsub0, addnsub1, signa, signb,
clk, aclr, ena, dataout, accoverflow,
devclrn, devpor);
`define ADD 1'b1
`define SUB 1'b0
parameter operation_mode = "output_only";
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter dataout_width = 72;
parameter addnsub0_clock = "none";
parameter addnsub1_clock = "none";
parameter zeroacc_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter output_clock = "none";
parameter addnsub0_clear = "none";
parameter addnsub1_clear = "none";
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