stratix_atoms.v

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   parameter power_up       = "low";
   parameter cin_used       = "false";
   parameter cin0_used      = "false";
   parameter cin1_used      = "false";
   parameter output_mode    = "comb_only";
   parameter lpm_type       = "stratix_lcell";
   parameter x_on_violation = "on";
   
   input     dataa, datab, datac, datad;
   input     clk, aclr, aload, sclr, sload, ena; 
   input     cin, cin0, cin1,  inverta, regcascin;
   input     devclrn, devpor ;
   output    cout, cout0, cout1, regout, combout;
   wire      dffin, qfbkin;
   
   stratix_asynch_lcell lecomb (.dataa(dataa), .datab(datab), 
				.datac(datac), .datad(datad),
				.cin(cin), .cin0(cin0), .cin1(cin1), 
				.inverta(inverta), .qfbkin(qfbkin),
				.regin(dffin), .combout(combout),
				.cout(cout), .cout0(cout0), .cout1(cout1));
   defparam  lecomb.operation_mode = operation_mode;
   defparam  lecomb.sum_lutc_input = sum_lutc_input;
   defparam  lecomb.cin_used = cin_used;
   defparam  lecomb.cin0_used = cin0_used;
   defparam  lecomb.cin1_used = cin1_used;
   defparam  lecomb.lut_mask = lut_mask;
   
   stratix_lcell_register lereg (.clk(clk), .aclr(aclr), .aload(aload),
				 .sclr(sclr), .sload(sload), .ena(ena), 
				 .datain(dffin), 
				 .datac(datac), .regcascin(regcascin),
				 .devclrn(devclrn), .devpor(devpor), 
				 .regout(regout), .qfbkout(qfbkin));
   defparam  lereg.synch_mode = synch_mode;
   defparam  lereg.register_cascade_mode = register_cascade_mode;
   defparam  lereg.power_up = power_up;
   defparam  lereg.x_on_violation = x_on_violation;
   
endmodule


///////////////////////////////////////////////////////////////////////////////
//
//                              STRATIX_ASYNCH_IO
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps

module stratix_asynch_io (datain, oe, regin, ddioregin, padio, delayctrlin, combout, 
			  regout, ddioregout);
   
   input datain, oe;
   input regin, ddioregin;
   input delayctrlin;
   output combout;
   output regout, ddioregout;
   inout  padio;
   
   parameter operation_mode = "input";
   parameter bus_hold = "false";
   parameter open_drain_output = "false";
   parameter phase_shift_delay = 0;
   
   reg 	     prev_value;
   
   reg 	     tmp_padio, tmp_combout;
   reg 	     buf_control;
   reg combout_tmp;

   integer dqs_delay;
   
   buf(datain_in, datain);
   buf(oe_in, oe);
   buf (delayctrlin_ipd, delayctrlin);
   
   tri 	     padio_tmp;
   
   specify
      (padio => combout) = (0,0);
      (datain => padio) = (0, 0);
      (posedge oe => (padio +: padio_tmp)) = (0, 0);
      (negedge oe => (padio +: 1'bz)) = (0, 0);
      (ddioregin => ddioregout) = (0, 0);
      (regin => regout) = (0, 0);
   endspecify
   
   initial
      begin
	 prev_value = 'b0;
	 tmp_padio = 'bz;
         dqs_delay = phase_shift_delay;
      end
  
        always @(delayctrlin_ipd)
        begin
            if (delayctrlin_ipd == 1'b1)
                dqs_delay = phase_shift_delay;
            else if (delayctrlin_ipd == 1'b0)
                dqs_delay = 0;
            else begin
                $display($time, " Warning: Illegal value detected on 'delayctrlin' input.");
                dqs_delay = 0;
            end
        end
 
	always @(datain_in or oe_in or padio)
	begin
		if (bus_hold == "true" )
		begin
			buf_control = 'b1;
			if ( operation_mode == "output" || operation_mode == "bidir")
			begin
				if ( oe_in == 1)
				begin
					if ( open_drain_output == "true" )
					begin
						if (datain_in == 0)
						begin
							tmp_padio =  1'b0;
							prev_value = 1'b0;
						end
						else if (datain_in == 1'bx)
						begin
							tmp_padio = 1'bx;
							prev_value = 1'bx;
						end
						else   // output of tri is 'Z'
						begin
							if ( operation_mode == "bidir")
								prev_value = padio;
							
							tmp_padio = 1'bz;
						end
					end  
					else  // open drain_output = false;
					begin
						tmp_padio = datain_in;
						prev_value = datain_in;
					end
				end   
				else if ( oe_in == 0 )
				begin
					if (operation_mode == "bidir")
						prev_value = padio;

					tmp_padio = 1'bz;
				end
				else   // oe == 'X' 
				begin
					tmp_padio = 1'bx;
					prev_value = 1'bx;
				end
			end
			
			if ( operation_mode == "output")
				tmp_combout = 1'bz;
			else
				tmp_combout = padio;
		end
		else    // bus hold is false
		begin
			buf_control = 'b0;
			if ( operation_mode == "input")
			begin
				tmp_combout = padio;
			end
			else if (operation_mode == "output" || operation_mode == "bidir")
			begin
				if ( operation_mode  == "bidir")
					tmp_combout = padio;
				
				if ( oe_in == 1 )
				begin
					if ( open_drain_output == "true" )
					begin
						if (datain_in == 0)
							tmp_padio = 1'b0;
						else if ( datain_in == 1'bx)
							tmp_padio = 1'bx;
						else
							tmp_padio = 1'bz;
					end
					else
						tmp_padio = datain_in;
				end
				else if ( oe_in == 0 )
					tmp_padio = 1'bz;
				else
					tmp_padio = 1'bx;
			end
			else
				$display ("Error: Invalid operation_mode specified in stratix io atom!\n");
		end
        combout_tmp <= #(dqs_delay) tmp_combout;
	end
   
   bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control);  //weak value
   pmos (padio_tmp, tmp_padio, 'b0);
//   pmos (combout, tmp_combout, 'b0);
   pmos (combout, combout_tmp, 'b0);
   pmos (padio, padio_tmp, 'b0);
   and (regout, regin, 1'b1);
   and (ddioregout, ddioregin, 1'b1);

endmodule

///////////////////////////////////////////////////////////////////////////////
//
//                             STRATIX_IO_REGISTER
//
///////////////////////////////////////////////////////////////////////////////

module  stratix_io_register (clk, datain, ena, 
			     sreset, areset, 
			     devclrn, devpor, regout);
   parameter	async_reset = "none";
   parameter 	sync_reset = "none";
   parameter 	power_up = "low";
   
   input 	clk, ena, datain;
   input 	areset, sreset;
   input 	devclrn, devpor ;
   output 	regout;
   
   reg 		iregout;
   wire 	clk_in;
   wire 	reset, is_areset_clear, is_areset_preset;
   
   reg 		datain_viol;
   reg 		sreset_viol;
   reg 		ena_viol;
   reg 		violation;
   
   reg 		clk_last_value;
   
   buf (clk_in, clk);
   buf (idatain, datain);
   buf (iareset, areset);
   buf (isreset, sreset);
   buf (iena, ena);
   
   assign reset = devpor && devclrn && !(iareset && async_reset != "none") && (iena);
   
   assign is_areset_clear = (async_reset == "clear")?1'b1:1'b0;
   assign is_areset_preset = (async_reset == "preset")?1'b1:1'b0;

   specify
      
      $setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
      $setuphold (posedge clk &&& reset, sreset, 0, 0, sreset_viol) ;
      $setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
      
      (posedge clk => (regout +: iregout)) = 0 ;
      
      if (is_areset_clear == 1'b1)
	 (posedge areset => (regout +: 1'b0)) = (0,0);
      if ( is_areset_preset == 1'b1)
	 (posedge areset => (regout +: 1'b1)) = (0,0);
      
   endspecify
   
   initial
      begin
//	 clk_last_value = 0;
	 violation = 0;
	 if (power_up == "low")
	    iregout = 'b0;
	 else if (power_up == "high")
	    iregout = 'b1;
      end
   
   always @ (datain_viol or sreset_viol or ena_viol)
      begin
	 violation = 1;
      end
   
   always @ (clk_in or posedge iareset or negedge devclrn or negedge devpor or posedge violation)
      begin
	 if (violation == 1'b1)
        begin
	   violation = 0;
	   iregout = 'bx;
	end
	else if (devpor == 'b0)
	begin
	    if (power_up == "low")
	        iregout = 'b0;
	    else if (power_up == "high")
		iregout = 'b1;
	end
	else if (devclrn == 'b0)
		iregout = 'b0;
	else if (async_reset == "clear" && iareset == 'b1) 
	      iregout = 'b0 ;
	else if (async_reset == "preset" && iareset == 'b1 )
			   iregout = 'b1;
	else if (iena == 'b1 && clk_in == 'b1 && clk_last_value == 'b0)
	begin
		   if (sync_reset == "clear" && isreset == 'b1)
		      iregout = 'b0 ;
	else if (sync_reset == "preset" && isreset == 'b1)
	      iregout = 'b1;
	else
	   iregout = idatain ;
				end
	 clk_last_value = clk_in;
      end
   and (regout, iregout, 'b1) ;
endmodule

///////////////////////////////////////////////////////////////////////////////
//
//                                STRATIX_IO
//
///////////////////////////////////////////////////////////////////////////////

module stratix_io (datain, ddiodatain, oe, outclk, outclkena,
		   inclk, inclkena, areset, sreset, delayctrlin, devclrn, devpor, devoe,
		   padio, combout, regout, ddioregout);
   
   parameter operation_mode = "input";
   parameter ddio_mode = "none";
   parameter open_drain_output = "false";
   parameter bus_hold = "false";
   
   parameter output_register_mode = "none";
   parameter output_async_reset = "none";
   parameter output_sync_reset = "none";
   parameter output_power_up = "low";
   parameter tie_off_output_clock_enable = "false";
   
   parameter oe_register_mode = "none";
   parameter oe_async_reset = "none";
   parameter oe_sync_reset = "none";
   parameter oe_power_up = "low";
   parameter tie_off_oe_clock_enable = "false";
   
   parameter input_register_mode = "none";
   parameter input_async_reset = "none";
   parameter input_sync_reset = "none";
   parameter input_power_up = "low";
   
   parameter extend_oe_disable = "false";
 
   parameter sim_dll_phase_shift = 0;
   parameter sim_dqs_input_frequency = 10000;
 
   // LOCAL PARAMETERS

   parameter phase_shift_delay = (sim_dll_phase_shift * sim_dqs_input_frequency)/360;

   inout     padio;
   input     datain, ddiodatain;
   input     oe, outclk, outclkena, inclk, inclkena;
   input     areset, sreset, delayctrlin;
   input     devclrn, devpor, devoe;
   output    combout, regout, ddioregout;
   
   wire      oe_reg_out, oe_pulse_reg_out;
   wire      in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out;
   wire      out_reg_out, out_ddio_reg_out;
   
   wire      out_clk_ena, oe_clk_ena;
   
   wire      tmp_datain;
   wire      ddio_data;
   wire      oe_out;
   wire      outclk_delayed;
  

   assign out_clk_ena = (tie_off_output_clock_enable == "false") ? outclkena : 1'b1;
   assign oe_clk_ena = (tie_off_oe_clock_enable == "false") ? outclkena : 1'b1;
   
   //input register
   stratix_io_register in_reg  (.regout(in_reg_out), .clk(inclk), 
				.ena(inclkena), .datain(padio), 
				.areset(areset), .sreset(sreset), 
				.devpor(devpor), .devclrn(devclrn));
   defparam  in_reg.async_reset = input_async_reset;
   defparam  in_reg.sync_reset = input_sync_reset;
   defparam  in_reg.power_up = input_power_up;
   
   // in_ddio0_reg
   stratix_io_register in_ddio0_reg (.regout(in_ddio0_reg_out), .clk(!inclk), 
				     .ena (inclkena), .datain(padio), 
				     .areset(areset), .sreset(sreset),
				     .devpor(devpor), .devclrn(devclrn));
   defparam  in_ddio0_reg.async_reset = input_async_reset;
   defparam  in_ddio0_reg.sync_reset = input_sync_reset;
   defparam  in_ddio0_reg.power_up = input_power_up;
   
   // in_ddio1_reg
   stratix_io_register in_ddio1_reg (.regout(in_ddio1_reg_out), .clk(inclk), 
				     .ena(inclkena), .datain(in_ddio0_reg_out),
				     .areset(areset), .sreset(1'b0),
				     .devpor(devpor), .devclrn(devclrn));
   defparam  in_ddio1_reg.async_reset = input_async_reset;
   defparam  in_ddio1_reg.sync_reset = "none"; // this register has no sync_reset
   defparam  in_ddio1_reg.power_up = input_power_up;
   
   // out_reg
   stratix_io_register out_reg (.regout(out_reg_out), .clk(outclk), 
				.ena(out_clk_ena), .datain(datain), 
				.areset(areset), .sreset(sreset),