📄 stratix_atoms.v
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digit[m] = digit[m] + 9;
end
str_to_bin = {digit[1], digit[2], digit[3], digit[4]};
end
endfunction
function lut4 ;
input [4*8:1] lut_mask ;
input dataa, datab, datac, datad ;
reg [15:0] mask ;
reg prev_lut4;
reg dataa_new, datab_new, datac_new, datad_new;
integer h, i, j, k;
integer hn, in, jn, kn;
integer exitloop;
integer check_prev;
begin
mask = str_to_bin (lut_mask) ;
begin
if ((datad === 1'bx) || (datad === 1'bz))
begin
datad_new = 1'b0;
hn = 2;
end
else
begin
datad_new = datad;
hn = 1;
end
check_prev = 0;
exitloop = 0;
h = 1;
while ((h <= hn) && (exitloop == 0))
begin
if ((datac === 1'bx) || (datac === 1'bz))
begin
datac_new = 1'b0;
in = 2;
end
else
begin
datac_new = datac;
in = 1;
end
i = 1;
while ((i <= in) && (exitloop ==0))
begin
if ((datab === 1'bx) || (datab === 1'bz))
begin
datab_new = 1'b0;
jn = 2;
end
else
begin
datab_new = datab;
jn = 1;
end
j = 1;
while ((j <= jn) && (exitloop ==0))
begin
if ((dataa === 1'bx) || (dataa === 1'bz))
begin
dataa_new = 1'b0;
kn = 2;
end
else
begin
dataa_new = dataa;
kn = 1;
end
k = 1;
while ((k <= kn) && (exitloop ==0))
begin
case ({datad_new,
datac_new,
datab_new,
dataa_new})
4'b0000: lut4 = mask[0] ;
4'b0001: lut4 = mask[1] ;
4'b0010: lut4 = mask[2] ;
4'b0011: lut4 = mask[3] ;
4'b0100: lut4 = mask[4] ;
4'b0101: lut4 = mask[5] ;
4'b0110: lut4 = mask[6] ;
4'b0111: lut4 = mask[7] ;
4'b1000: lut4 = mask[8] ;
4'b1001: lut4 = mask[9] ;
4'b1010: lut4 = mask[10] ;
4'b1011: lut4 = mask[11] ;
4'b1100: lut4 = mask[12] ;
4'b1101: lut4 = mask[13] ;
4'b1110: lut4 = mask[14] ;
4'b1111: lut4 = mask[15] ;
default: $display ("Warning: Reached forbidden part of lcell code.\n");
endcase
if ((check_prev == 1) && (prev_lut4 !==lut4))
begin
lut4 = 1'bx;
exitloop = 1;
end
else
begin
check_prev = 1;
prev_lut4 = lut4;
end
k = k + 1;
dataa_new = 1'b1;
end // loop a
j = j + 1;
datab_new = 1'b1;
end // loop b
i = i + 1;
datac_new = 1'b1;
end // loop c
h = h + 1;
datad_new = 1'b1;
end // loop d
end
end
endfunction
always @(idatad or idatac or idatab or idataa or icin or
icin0 or icin1 or iinverta or qfbkin)
begin
if (iinverta === 'b1) //invert dataa
inverta_dataa = !idataa;
else
inverta_dataa = idataa;
if (operation_mode == "normal")
begin
if (sum_lutc_input == "datac")
begin
data = lut4(lut_mask, inverta_dataa, idatab, idatac, idatad);
end
else if ( sum_lutc_input == "cin" )
begin
if (cin0_used == "true" || cin1_used == "true")
begin
if (cin_used == "true")
data = (icin === 'b0) ?
lut4(lut_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(lut_mask,
inverta_dataa,
idatab,
icin1,
idatad);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(lut_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(lut_mask,
inverta_dataa,
idatab,
icin1,
idatad);
end
else
data = lut4(lut_mask, inverta_dataa, idatab, icin, idatad);
end
else if( sum_lutc_input == "qfbk")
begin
data = lut4(lut_mask, inverta_dataa, idatab, qfbkin, idatad);
end
end
else if (operation_mode == "arithmetic")
begin
// sum LUT
if (sum_lutc_input == "datac")
begin
data = lut4(lut_mask, inverta_dataa, idatab, idatac, 'b1);
end
else if ( sum_lutc_input == "cin" )
begin
if (cin0_used == "true" || cin1_used == "true")
begin
if (cin_used == "true")
data = (icin === 'b0) ?
lut4(lut_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(lut_mask,
inverta_dataa,
idatab,
icin1,
'b1);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(lut_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(lut_mask,
inverta_dataa,
idatab,
icin1,
'b1);
end
else
if ( cin_used == "true")
data = lut4(lut_mask, inverta_dataa, idatab, icin, 'b1);
else // cin is not used, inverta is used as cin
data = lut4(lut_mask, inverta_dataa, idatab,
iinverta, 'b1);
end
else if( sum_lutc_input == "qfbk")
begin
data = lut4(lut_mask, inverta_dataa, idatab, qfbkin, 'b1);
end
// carry LUT
icout0 = lut4(lut_mask, inverta_dataa, idatab, icin0, 'b0);
icout1 = lut4(lut_mask, inverta_dataa, idatab, icin1, 'b0);
if ( cin_used == "true" )
begin
if (cin0_used == "true" || cin1_used == "true")
icout = (icin === 'b0) ? icout0 : icout1;
else
icout = lut4(lut_mask, inverta_dataa, idatab, icin, 'b0);
end
else // inverta is used in place of cin
begin
if (cin0_used == "true" || cin1_used == "true")
icout = (iinverta === 'b0) ? icout0 : icout1;
else
icout = lut4(lut_mask,
inverta_dataa, idatab, iinverta, 'b0);
end
end
end
and (combout, data, 'b1) ;
and (cout, icout, 'b1) ;
and (cout0, icout0, 'b1) ;
and (cout1, icout1, 'b1) ;
and (regin, data, 'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_LCELL_REGISTER
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lcell_register (clk, aclr, aload, sclr, sload, ena, datain,
datac, regcascin, devclrn, devpor, regout,
qfbkout) ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
input clk, ena, aclr, aload, sclr, sload;
input datain, datac, regcascin;
input devclrn, devpor ;
output regout, qfbkout;
reg iregout;
wire reset;
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (x_on_violation == "on")
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload or negedge devclrn
or negedge devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout = 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
else if (devclrn == 'b0)
iregout = 'b0;
else if (iaclr === 'b1)
iregout = 'b0 ;
else if (iaload === 'b1)
iregout = idatac;
else if (iena === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (synch_mode == "on" )
begin
if (isclr === 'b1)
iregout = 'b0 ;
else if (isload === 'b1)
iregout = idatac;
else if (register_cascade_mode == "on")
iregout = iregcascin;
else
iregout = idatain;
end
else if (register_cascade_mode == "on")
iregout = iregcascin;
else
iregout = idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 'b1);
and (qfbkout, iregout, 'b1);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_LCELL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lcell (clk, dataa, datab, datac, datad, aclr, aload,
sclr, sload, ena, cin, cin0, cin1,
inverta, regcascin,
devclrn, devpor,
combout, regout, cout, cout0, cout1) ;
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
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