_primary.vhd

来自「一个非常好的dc使用书籍 一个非常好的dc使用书籍」· VHDL 代码 · 共 35 行

library verilog;
use verilog.vl_types.all;
entity stratixgx_hssi_rx_sync_sm is
    generic(
        synchronization_mode: string  := "XAUI";
        use_8b_10b_mode : string  := "true";
        channel_width   : integer := 10;
        \LOSS_OF_SYNC\  : integer := 1;
        \COMMA_DET_1\   : integer := 2;
        \COMMA_DET_2\   : integer := 4;
        \COMMA_DET_3\   : integer := 8;
        \GE_ACQ_SYNC_1\ : integer := 16;
        \GE_ACQ_SYNC_2\ : integer := 32;
        \SYNC_ACQ_1\    : integer := 64;
        \SYNC_ACQ_2\    : integer := 128;
        \SYNC_ACQ_2A\   : integer := 256;
        \SYNC_ACQ_3\    : integer := 512;
        \SYNC_ACQ_3A\   : integer := 1024;
        \SYNC_ACQ_4\    : integer := 2048;
        \SYNC_ACQ_4A\   : integer := 4096
    );
    port(
        clk             : in     vl_logic;
        softreset       : in     vl_logic;
        enacdetin       : in     vl_logic;
        enacdetcustom   : in     vl_logic;
        invalidcode     : in     vl_logic;
        patterndetect   : in     vl_logic;
        kchar           : in     vl_logic;
        enacdet         : out    vl_logic;
        encdtsync       : out    vl_logic;
        syncstatus      : out    vl_logic
    );
end stratixgx_hssi_rx_sync_sm;