_primary.vhd

一个非常好的dc使用书籍 一个非常好的dc使用书籍

library verilog;
use verilog.vl_types.all;
entity stratixgx_parity_6b is
    port(
        parity_in       : in     vl_logic;
        parity_4b_odd   : in     vl_logic;
        parity_4b_even  : in     vl_logic;
        parity_4b_even_3: in     vl_logic;
        parity_4b_odd_c : in     vl_logic;
        data_in         : in     vl_logic_vector(5 downto 0);
        disp_err_d      : out    vl_logic;
        k28_6b_even     : out    vl_logic;
        k28_6b_odd      : out    vl_logic;
        k_6b            : out    vl_logic;
        other_k_6b_even : out    vl_logic;
        other_k_6b_odd  : out    vl_logic;
        s_6b            : out    vl_logic;
        parity_6b_int   : out    vl_logic;
        invalid_6b_code : out    vl_logic
    );
end stratixgx_parity_6b;