ads2.v

ADS8325caiyang konfgzhi

module ads2 (clk,enable,din,dclock,dout,cs,cs1);
input       enable,clk;
input       din;
output      cs,dclock,cs1;
output       dout;
reg         cs,cs1,dclock,dout;      
reg [6:0]   cnt;
reg [1:0]    current_state,next_state;//状态寄存器
reg [15:0]    counter1;//计数器
parameter   samping=3'b000,converting=3'b001, power_down=3'b010;
always @ (posedge clk ) 
  begin
    begin
         if(enable==1'b0)
              cnt<=cnt+1;
         else 
           cnt<=7'b0;
    end
    dclock<=cnt[6];
end
always @ (posedge  dclock)
   begin
      if (!enable)
          begin
               if(counter1<=5'b10101)
                        cs<=0; 
               else   cs<=1 ;  
          end
     else     cs<=1;  
   end
always @ (posedge  dclock)
   begin
      if (!enable)
          begin
               if(counter1>=5'b00101&&counter1<=5'b10101)
                        cs1<=0; 
               else   cs1<=1 ;  
          end
     else     cs1<=1;  
   end
always @ (posedge dclock)
   begin
      if (!enable)
          begin
              if(counter1<=400)
                     counter1<=counter1+1;
              else   counter1<=0;
          end
      else counter1<=0;
  end
always @ (current_state)
   begin
     case (current_state) 
         samping:   if (counter1<=5'b00100) 
                         next_state=samping;
                    else  next_state= converting;
         converting:     if (counter1<=5'b10101 && counter1>=5'b00100) 
                              next_state= converting;
                          else  next_state=power_down ;
         power_down:   if (counter1<=400 && counter1>=5'b10101)  
                            next_state=power_down ;
                       else   next_state= samping;
         default:  next_state=power_down;
         endcase
   end
always @ (negedge dclock )
   begin
        if(!enable)
          current_state<=next_state;
        else current_state<=power_down;
   end
always @ (current_state )
   begin
     case (current_state) 
         samping:          dout<='bz; 
         converting:       dout<=din;       
         power_down:       dout<='bz;
         default:          dout<='bz; 
    endcase
   end
endmodule