📄 flashwrite.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY flashwrite IS
generic (databyteshu: integer :=4);----需要保存数据字节数
PORT (clkin : IN std_logic;
dataram: in std_logic_vector(7 downto 0);
clkout: buffer std_logic ;
dataout: inout std_logic;
ramread: out std_logic;
flashwrite:in std_logic;
addrram: out integer range 0 to 9 );
END flashwrite;
----------------------------------------------------------
ARCHITECTURE flashwrite OF flashwrite IS
BEGIN
------------产生相位差四分之一周期的时钟----------
PROCESS(clkin,dataram)
VARIABLE write: std_logic :='0';
VARIABLE ramdatatemp: std_logic_vector(7 downto 0); -----临时储存RAM数据
VARIABLE temp1: INTEGER range 0 to 4:=0;-----产生flash周期及
VARIABLE temp2: INTEGER :=0; -------整个计数
VARIABLE temp_flashwrite:std_logic;
VARIABLE temp4: INTEGER range 0 to 31:=0; -----标记写到了哪个字节
VARIABLE temp5: INTEGER range 0 to 1023;-------
VARIABLE temp6: INTEGER range 0 to 15:=0; ---------标志字节位
BEGIN
---------------------------检验写信号-------------------------
-------------------------------------------------------------
ramdatatemp:=dataram;
if rising_edge(clkin) then
temp_flashwrite:=flashwrite;
end if;
if(clkin'EVENT AND clkin='1') THEN
temp1:=temp1+1;
temp2:=temp2+1;
if(flashwrite='1' and temp_flashwrite='0')then
write:='1';
temp2:=0;
temp1:=0;
temp4:=0;
temp6:=0;
end if;
IF (temp1=1) THEN
clkout<= '1' and write;
elsif (temp1=2)then
clkout<= '1' and write;
elsif (temp1=3)then
clkout<='0';
else
clkout<='0';
temp1:=0;
END IF;
if temp2<117 then
case temp2 is
when 5 => dataout<= '1';
ramread<='0'; ------------开始状态锁闭ram
when 14 => dataout<= '0'; ---------------------------------------------
-------------------------------------------------
when 16 => dataout<= '1';-----------------------------------------------
when 20 => dataout<= '0';
when 24 => dataout<= '1';
when 28 => dataout<= '0';
----------------------------------------------------
when 32 => dataout<= '0';
when 36 => dataout<= '0';
when 40 => dataout<= '0';
-------------------------------------------------------------
when 44 => dataout<= '0'; ---写命令
when 47 => dataout<= 'Z';
--------------------------地址字节(高位)----------------------------
when 52 => dataout<= '0';
when 56 => dataout<= '0';
when 60 => dataout<= '0';
when 64 => dataout<= '0';
when 68 => dataout<= '0';
when 72 => dataout<= '0';
when 76 => dataout<= '0';
when 80 => dataout<= '0';
when 84 => dataout<= 'Z';
--------------------------地址字节(低位)----------------------------
when 88 => dataout<= '0';
when 92 => dataout<= '0';
when 96 => dataout<= '0';
when 100 => dataout<= '0';
when 104 => dataout<= '0';
when 108 => dataout<= '0';
when 112 => dataout<= '0';
when 116 => dataout<= '1';
when 120 => dataout<= 'Z';
temp5:=124;
when others => null;
end case;
end if;
-----------------------------写入数据字节------------------------
if(temp2=116+temp4*36+4)then
dataout<= 'Z';
end if;
if(temp2=116+temp4*36+1)then
addrram<=temp4;
ramread<='1';
ramdatatemp:=dataram;
end if;
if(temp2=temp5)then
dataout<=ramdatatemp(temp6);------------------------------------------------------
temp6:=temp6+1;
temp5:=temp5+4;
end if;
if temp6>7 then
temp6:=0;
temp5:=116+temp4*36+44;
temp4:=temp4+1;
if temp4=databyteshu then
temp4:=0;
temp5:=124;
end if;
end if;
------------------------收最后一个ack信号-----------------------
if temp2=116+databyteshu*36+4 then
dataout<='Z';
end if;
------------------------停止信号产生--------------
if temp2=116+databyteshu*36+8 then
dataout<='0';
end if;
if temp2=116+databyteshu*36+10 then
dataout<='1';
ramread<='0';
end if;
-----------------------写结束后释放总线关闭时钟-----------------------
if temp2=116+databyteshu*36+12 then
dataout<='Z';
write:='0';-----------------此后时钟始终为零注意复用
end if;
---------------------------------------------------------------------
END IF;
END PROCESS;
END flashwrite;
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