count_8.v

来自「second.rar 这个做的是一秒表计时程序」· Verilog 代码 · 共 25 行

module count_8 (clk, reset, temp, q);

input clk, reset;
output temp;
output [7:0] q;

reg [7:0] q;
reg temp;

always @ (posedge clk or posedge reset)
   begin
	if (reset == 1)
		begin
			q <= 0;
			temp <= 0;
	    end
	else
			begin
			q = q + 1;
			if (q == 8'h00)
				temp <= ~temp;
			end
	end
endmodule