second_count.tan.qmsg

second.rar 这个做的是一秒表计时程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register count_16:count_16_inst\|q\[5\] register mux_4_1:mux_4_1_inst\|dataout\[1\] 108.74 MHz 9.196 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 108.74 MHz between source register \"count_16:count_16_inst\|q\[5\]\" and destination register \"mux_4_1:mux_4_1_inst\|dataout\[1\]\" (period= 9.196 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.522 ns + Longest register register " "Info: + Longest register to register delay is 2.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_16:count_16_inst\|q\[5\] 1 REG LC_X25_Y9_N6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y9_N6; Fanout = 8; REG Node = 'count_16:count_16_inst\|q\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count_16:count_16_inst|q[5] } "NODE_NAME" } } { "count_16.v" "" { Text "D:/lts/library/Second/count_16.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.114 ns) 1.400 ns mux_4_1:mux_4_1_inst\|Mux2~25 2 COMB LC_X25_Y10_N2 1 " "Info: 2: + IC(1.286 ns) + CELL(0.114 ns) = 1.400 ns; Loc. = LC_X25_Y10_N2; Fanout = 1; COMB Node = 'mux_4_1:mux_4_1_inst\|Mux2~25'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { count_16:count_16_inst|q[5] mux_4_1:mux_4_1_inst|Mux2~25 } "NODE_NAME" } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.712 ns) + CELL(0.114 ns) 2.226 ns mux_4_1:mux_4_1_inst\|Mux2~26 3 COMB LC_X26_Y10_N3 1 " "Info: 3: + IC(0.712 ns) + CELL(0.114 ns) = 2.226 ns; Loc. = LC_X26_Y10_N3; Fanout = 1; COMB Node = 'mux_4_1:mux_4_1_inst\|Mux2~26'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.826 ns" { mux_4_1:mux_4_1_inst|Mux2~25 mux_4_1:mux_4_1_inst|Mux2~26 } "NODE_NAME" } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.522 ns mux_4_1:mux_4_1_inst\|dataout\[1\] 4 REG LC_X26_Y10_N4 7 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.522 ns; Loc. = LC_X26_Y10_N4; Fanout = 7; REG Node = 'mux_4_1:mux_4_1_inst\|dataout\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { mux_4_1:mux_4_1_inst|Mux2~26 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.342 ns ( 13.56 % ) " "Info: Total cell delay = 0.342 ns ( 13.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.180 ns ( 86.44 % ) " "Info: Total interconnect delay = 2.180 ns ( 86.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { count_16:count_16_inst|q[5] mux_4_1:mux_4_1_inst|Mux2~25 mux_4_1:mux_4_1_inst|Mux2~26 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.522 ns" { count_16:count_16_inst|q[5] mux_4_1:mux_4_1_inst|Mux2~25 mux_4_1:mux_4_1_inst|Mux2~26 mux_4_1:mux_4_1_inst|dataout[1] } { 0.000ns 1.286ns 0.712ns 0.182ns } { 0.000ns 0.114ns 0.114ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.708 ns - Smallest " "Info: - Smallest clock skew is -0.708 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 15.659 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 15.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 16; CLK Node = 'clkin'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "second_count.v" "" { Text "D:/lts/library/Second/second_count.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|safe_q\[13\] 2 REG LC_X11_Y9_N5 4 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X11_Y9_N5; Fanout = 4; REG Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|safe_q\[13\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 178 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.423 ns) 4.065 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella13~COUT 3 COMB LC_X11_Y9_N5 2 " "Info: 3: + IC(0.516 ns) + CELL(0.423 ns) = 4.065 ns; Loc. = LC_X11_Y9_N5; Fanout = 2; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella13~COUT'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.939 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 139 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.143 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella14~COUT 4 COMB LC_X11_Y9_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 4.143 ns; Loc. = LC_X11_Y9_N6; Fanout = 2; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella14~COUT'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 147 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.221 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella15~COUT 5 COMB LC_X11_Y9_N7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 4.221 ns; Loc. = LC_X11_Y9_N7; Fanout = 1; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|counter_cella15~COUT'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 155 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.604 ns) 4.825 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|modulus_trigger 6 COMB LC_X11_Y9_N8 29 " "Info: 6: + IC(0.000 ns) + CELL(0.604 ns) = 4.825 ns; Loc. = LC_X11_Y9_N8; Fanout = 29; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|modulus_trigger'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.604 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 177 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.321 ns) + CELL(0.935 ns) 10.081 ns RLSifter_4:RLSifter_4_inst\|q\[3\] 7 REG LC_X24_Y12_N2 3 " "Info: 7: + IC(4.321 ns) + CELL(0.935 ns) = 10.081 ns; Loc. = LC_X24_Y12_N2; Fanout = 3; REG Node = 'RLSifter_4:RLSifter_4_inst\|q\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.256 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] } "NODE_NAME" } } { "RLSifter_4.v" "" { Text "D:/lts/library/Second/RLSifter_4.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 10.459 ns mux_4_1:mux_4_1_inst\|Mux4~13 8 COMB LC_X24_Y12_N2 4 " "Info: 8: + IC(0.000 ns) + CELL(0.378 ns) = 10.459 ns; Loc. = LC_X24_Y12_N2; Fanout = 4; COMB Node = 'mux_4_1:mux_4_1_inst\|Mux4~13'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.378 ns" { RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 } "NODE_NAME" } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.908 ns) + CELL(0.292 ns) 15.659 ns mux_4_1:mux_4_1_inst\|dataout\[1\] 9 REG LC_X26_Y10_N4 7 " "Info: 9: + IC(4.908 ns) + CELL(0.292 ns) = 15.659 ns; Loc. = LC_X26_Y10_N4; Fanout = 7; REG Node = 'mux_4_1:mux_4_1_inst\|dataout\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.192 ns ( 33.16 % ) " "Info: Total cell delay = 5.192 ns ( 33.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.467 ns ( 66.84 % ) " "Info: Total interconnect delay = 10.467 ns ( 66.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "15.659 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "15.659 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } { 0.000ns 0.000ns 0.722ns 0.516ns 0.000ns 0.000ns 0.000ns 4.321ns 0.000ns 4.908ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.078ns 0.078ns 0.604ns 0.935ns 0.378ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 16.367 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 16.367 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 16; CLK Node = 'clkin'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "second_count.v" "" { Text "D:/lts/library/Second/second_count.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|safe_q\[0\] 2 REG LC_X11_Y10_N2 4 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X11_Y10_N2; Fanout = 4; REG Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|safe_q\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 178 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.590 ns) 4.295 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|cmpr1_aeb_int~113 3 COMB LC_X11_Y10_N1 1 " "Info: 3: + IC(0.556 ns) + CELL(0.590 ns) = 4.295 ns; Loc. = LC_X11_Y10_N1; Fanout = 1; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|cmpr1_aeb_int~113'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.146 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.292 ns) 6.128 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|cmpr1_aeb_int~117 4 COMB LC_X10_Y9_N7 1 " "Info: 4: + IC(1.541 ns) + CELL(0.292 ns) = 6.128 ns; Loc. = LC_X10_Y9_N7; Fanout = 1; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|cmpr1_aeb_int~117'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.833 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.114 ns) 6.921 ns LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|modulus_trigger 5 COMB LC_X11_Y9_N8 29 " "Info: 5: + IC(0.679 ns) + CELL(0.114 ns) = 6.921 ns; Loc. = LC_X11_Y9_N8; Fanout = 29; COMB Node = 'LPM_fp:LPM_fp_inst\|lpm_counter:lpm_counter_component\|cntr_6ej:auto_generated\|modulus_trigger'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger } "NODE_NAME" } } { "db/cntr_6ej.tdf" "" { Text "D:/lts/library/Second/db/cntr_6ej.tdf" 177 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.303 ns) + CELL(0.935 ns) 12.159 ns count_8:count_8_inst\|temp 6 REG LC_X8_Y10_N2 17 " "Info: 6: + IC(4.303 ns) + CELL(0.935 ns) = 12.159 ns; Loc. = LC_X8_Y10_N2; Fanout = 17; REG Node = 'count_8:count_8_inst\|temp'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.238 ns" { LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp } "NODE_NAME" } } { "count_8.v" "" { Text "D:/lts/library/Second/count_8.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 16.367 ns count_16:count_16_inst\|q\[5\] 7 REG LC_X25_Y9_N6 8 " "Info: 7: + IC(3.497 ns) + CELL(0.711 ns) = 16.367 ns; Loc. = LC_X25_Y9_N6; Fanout = 8; REG Node = 'count_16:count_16_inst\|q\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.208 ns" { count_8:count_8_inst|temp count_16:count_16_inst|q[5] } "NODE_NAME" } } { "count_16.v" "" { Text "D:/lts/library/Second/count_16.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.046 ns ( 30.83 % ) " "Info: Total cell delay = 5.046 ns ( 30.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.321 ns ( 69.17 % ) " "Info: Total interconnect delay = 11.321 ns ( 69.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.367 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "16.367 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } { 0.000ns 0.000ns 0.745ns 0.556ns 1.541ns 0.679ns 4.303ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.114ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "15.659 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "15.659 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } { 0.000ns 0.000ns 0.722ns 0.516ns 0.000ns 0.000ns 0.000ns 4.321ns 0.000ns 4.908ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.078ns 0.078ns 0.604ns 0.935ns 0.378ns 0.292ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.367 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "16.367 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } { 0.000ns 0.000ns 0.745ns 0.556ns 1.541ns 0.679ns 4.303ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.114ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count_16.v" "" { Text "D:/lts/library/Second/count_16.v" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.144 ns + " "Info: + Micro setup delay of destination is 1.144 ns" {  } { { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "count_16.v" "" { Text "D:/lts/library/Second/count_16.v" 42 -1 0 } } { "mux_4_1.v" "" { Text "D:/lts/library/Second/mux_4_1.v" 10 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.522 ns" { count_16:count_16_inst|q[5] mux_4_1:mux_4_1_inst|Mux2~25 mux_4_1:mux_4_1_inst|Mux2~26 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.522 ns" { count_16:count_16_inst|q[5] mux_4_1:mux_4_1_inst|Mux2~25 mux_4_1:mux_4_1_inst|Mux2~26 mux_4_1:mux_4_1_inst|dataout[1] } { 0.000ns 1.286ns 0.712ns 0.182ns } { 0.000ns 0.114ns 0.114ns 0.114ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "15.659 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "15.659 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[13] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella13~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella14~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|counter_cella15~COUT LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger RLSifter_4:RLSifter_4_inst|q[3] mux_4_1:mux_4_1_inst|Mux4~13 mux_4_1:mux_4_1_inst|dataout[1] } { 0.000ns 0.000ns 0.722ns 0.516ns 0.000ns 0.000ns 0.000ns 4.321ns 0.000ns 4.908ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.078ns 0.078ns 0.604ns 0.935ns 0.378ns 0.292ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.367 ns" { clkin LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "16.367 ns" { clkin clkin~out0 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|safe_q[0] LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~113 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|cmpr1_aeb_int~117 LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated|modulus_trigger count_8:count_8_inst|temp count_16:count_16_inst|q[5] } { 0.000ns 0.000ns 0.745ns 0.556ns 1.541ns 0.679ns 4.303ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.114ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clkin 42 " "Warning: Circuit may not operate. Detected 42 non-operational path(s) clocked by clock \"clkin\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}