second_count.hier_info

second.rar 这个做的是一秒表计时程序

|second_count
clkin => clkin~0.IN1
reset_n => reset.IN3
key[0] => ~NO_FANOUT~
key[1] => ~NO_FANOUT~
key[2] => ~NO_FANOUT~
key[3] => ~NO_FANOUT~
key[4] => ~NO_FANOUT~
key[5] => ~NO_FANOUT~
key[6] => ~NO_FANOUT~
key[7] => ~NO_FANOUT~
key[8] => ~NO_FANOUT~
switch[3] => ~NO_FANOUT~
switch[2] => ~NO_FANOUT~
switch[1] => ~NO_FANOUT~
switch[0] => clk_enable.IN1
led[7] <= <GND>
led[6] <= <GND>
led[5] <= <GND>
led[4] <= <GND>
led[3] <= <GND>
led[2] <= <GND>
led[1] <= <GND>
led[0] <= <GND>
seven[0] <= decode_7:decode_7_inst.data_out
seven[1] <= decode_7:decode_7_inst.data_out
seven[2] <= decode_7:decode_7_inst.data_out
seven[3] <= decode_7:decode_7_inst.data_out
seven[4] <= decode_7:decode_7_inst.data_out
seven[5] <= decode_7:decode_7_inst.data_out
seven[6] <= decode_7:decode_7_inst.data_out
seven[7] <= decode_7:decode_7_inst.data_out
seven_sel[3] <= sel[0].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[2] <= sel[1].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[1] <= sel[2].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[0] <= sel[3].DB_MAX_OUTPUT_PORT_TYPE
mem_addr[0] <= <GND>
mem_addr[1] <= <GND>
mem_addr[2] <= <GND>
mem_addr[3] <= <GND>
mem_addr[4] <= <GND>
mem_addr[5] <= <GND>
mem_addr[6] <= <GND>
mem_addr[7] <= <GND>
mem_addr[8] <= <GND>
mem_addr[9] <= <GND>
mem_addr[10] <= <GND>
mem_addr[11] <= <GND>
mem_addr[12] <= <GND>
mem_addr[13] <= <GND>
mem_addr[14] <= <GND>
mem_addr[15] <= <GND>
mem_addr[16] <= <GND>
mem_addr[17] <= <GND>
mem_addr[18] <= <GND>
mem_addr[19] <= <GND>
mem_addr[20] <= <GND>
mem_data[0] <= mem_data~32
mem_data[1] <= mem_data~31
mem_data[2] <= mem_data~30
mem_data[3] <= mem_data~29
mem_data[4] <= mem_data~28
mem_data[5] <= mem_data~27
mem_data[6] <= mem_data~26
mem_data[7] <= mem_data~25
mem_data[8] <= mem_data~24
mem_data[9] <= mem_data~23
mem_data[10] <= mem_data~22
mem_data[11] <= mem_data~21
mem_data[12] <= mem_data~20
mem_data[13] <= mem_data~19
mem_data[14] <= mem_data~18
mem_data[15] <= mem_data~17
sram_be[0] <= <GND>
sram_be[1] <= <GND>
sram_rd <= <GND>
sram_wr <= <GND>
sram_sel <= <GND>
flash_oe <= <VCC>
flash_we <= <GND>
flash_cs <= <VCC>
lcd_data[0] <= lcd_data~15
lcd_data[1] <= lcd_data~14
lcd_data[2] <= lcd_data~13
lcd_data[3] <= lcd_data~12
lcd_data[4] <= lcd_data~11
lcd_data[5] <= lcd_data~10
lcd_data[6] <= lcd_data~9
lcd_data[7] <= lcd_data~8
lcd_cs1 <= <GND>
lcd_cs2 <= <GND>
lcd_di <= <GND>
lcd_e <= <GND>
lcd_reset <= <GND>
lcd_rw <= <GND>
ps2_clk <= <GND>
ps2_data <= <GND>
ps2_2_clk <= <GND>
ps2_2_data <= <GND>
rxd => ~NO_FANOUT~
txd <= <GND>
rxd_2 => ~NO_FANOUT~
txd_2 <= <GND>
motor_counter => ~NO_FANOUT~
motor_pwm <= <GND>
da_a0 <= <GND>
da_a1 <= <GND>
da_data[0] <= <GND>
da_data[1] <= <GND>
da_data[2] <= <GND>
da_data[3] <= <GND>
da_data[4] <= <GND>
da_data[5] <= <GND>
da_data[6] <= <GND>
da_data[7] <= <GND>
da_ldac_n <= <GND>
da_wr_n <= <GND>
ad_convst_n <= <GND>
ad_sclk <= <GND>
ad_din <= <GND>
ad_dout => ~NO_FANOUT~
ad_rfs <= <GND>
ad_tfs <= <GND>
usb_addr[0] <= <GND>
usb_addr[1] <= <GND>
usb_addr[2] <= <GND>
usb_addr[3] <= <GND>
usb_addr[4] <= <GND>
usb_addr[5] <= <GND>
usb_addr[6] <= <GND>
usb_addr[7] <= <GND>
usb_data[0] <= usb_data~31
usb_data[1] <= usb_data~30
usb_data[2] <= usb_data~29
usb_data[3] <= usb_data~28
usb_data[4] <= usb_data~27
usb_data[5] <= usb_data~26
usb_data[6] <= usb_data~25
usb_data[7] <= usb_data~24
usb_data[8] <= usb_data~23
usb_data[9] <= usb_data~22
usb_data[10] <= usb_data~21
usb_data[11] <= usb_data~20
usb_data[12] <= usb_data~19
usb_data[13] <= usb_data~18
usb_data[14] <= usb_data~17
usb_data[15] <= usb_data~16
usb_int => ~NO_FANOUT~
usb_rdy => ~NO_FANOUT~
usb_rst_n <= <GND>
usb_cs_n <= <GND>
usb_rd_n <= <GND>
usb_wr_n <= <GND>


|second_count|LPM_fp:LPM_fp_inst
clock => clock~0.IN1
cout <= lpm_counter:lpm_counter_component.cout
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
q[10] <= lpm_counter:lpm_counter_component.q
q[11] <= lpm_counter:lpm_counter_component.q
q[12] <= lpm_counter:lpm_counter_component.q
q[13] <= lpm_counter:lpm_counter_component.q
q[14] <= lpm_counter:lpm_counter_component.q
q[15] <= lpm_counter:lpm_counter_component.q


|second_count|LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component
clock => cntr_6ej:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_6ej:auto_generated.q[0]
q[1] <= cntr_6ej:auto_generated.q[1]
q[2] <= cntr_6ej:auto_generated.q[2]
q[3] <= cntr_6ej:auto_generated.q[3]
q[4] <= cntr_6ej:auto_generated.q[4]
q[5] <= cntr_6ej:auto_generated.q[5]
q[6] <= cntr_6ej:auto_generated.q[6]
q[7] <= cntr_6ej:auto_generated.q[7]
q[8] <= cntr_6ej:auto_generated.q[8]
q[9] <= cntr_6ej:auto_generated.q[9]
q[10] <= cntr_6ej:auto_generated.q[10]
q[11] <= cntr_6ej:auto_generated.q[11]
q[12] <= cntr_6ej:auto_generated.q[12]
q[13] <= cntr_6ej:auto_generated.q[13]
q[14] <= cntr_6ej:auto_generated.q[14]
q[15] <= cntr_6ej:auto_generated.q[15]
cout <= cntr_6ej:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|second_count|LPM_fp:LPM_fp_inst|lpm_counter:lpm_counter_component|cntr_6ej:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT


|second_count|decode_7:decode_7_inst
data_in[0] => Decoder0.IN3
data_in[1] => Decoder0.IN2
data_in[2] => Decoder0.IN1
data_in[3] => Decoder0.IN0
data_out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE


|second_count|mux_4_1:mux_4_1_inst
datain[0] => Mux3.IN19
datain[1] => Mux2.IN19
datain[2] => Mux1.IN19
datain[3] => Mux0.IN19
datain[4] => Mux3.IN18
datain[5] => Mux2.IN18
datain[6] => Mux1.IN18
datain[7] => Mux0.IN18
datain[8] => Mux3.IN17
datain[9] => Mux2.IN17
datain[10] => Mux1.IN17
datain[11] => Mux0.IN17
datain[12] => Mux3.IN16
datain[13] => Mux2.IN16
datain[14] => Mux1.IN16
datain[15] => Mux0.IN16
dataout[0] <= dataout[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= dataout[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= dataout[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= dataout[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= <GND>
dataout[5] <= <GND>
dataout[6] <= <GND>
dataout[7] <= <GND>
dataout[8] <= <GND>
dataout[9] <= <GND>
dataout[10] <= <GND>
dataout[11] <= <GND>
dataout[12] <= <GND>
dataout[13] <= <GND>
dataout[14] <= <GND>
dataout[15] <= <GND>
sel[0] => Mux0.IN15
sel[0] => Mux1.IN15
sel[0] => Mux2.IN15
sel[0] => Mux3.IN15
sel[0] => Mux4.IN19
sel[1] => Mux0.IN14
sel[1] => Mux1.IN14
sel[1] => Mux2.IN14
sel[1] => Mux3.IN14
sel[1] => Mux4.IN18
sel[2] => Mux0.IN13
sel[2] => Mux1.IN13
sel[2] => Mux2.IN13
sel[2] => Mux3.IN13
sel[2] => Mux4.IN17
sel[3] => Mux0.IN12
sel[3] => Mux1.IN12
sel[3] => Mux2.IN12
sel[3] => Mux3.IN12
sel[3] => Mux4.IN16


|second_count|RLSifter_4:RLSifter_4_inst
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[3]~reg0.CLK
reset => q[2]~reg0.ACLR
reset => q[1]~reg0.ACLR
reset => q[0]~reg0.PRESET
reset => q[3]~reg0.ACLR
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|second_count|count_8:count_8_inst
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => temp~reg0.CLK
clk => q[7]~reg0.CLK
reset => q[6]~reg0.ACLR
reset => q[5]~reg0.ACLR
reset => q[4]~reg0.ACLR
reset => q[3]~reg0.ACLR
reset => q[2]~reg0.ACLR
reset => q[1]~reg0.ACLR
reset => q[0]~reg0.ACLR
reset => temp~reg0.ACLR
reset => q[7]~reg0.ACLR
temp <= temp~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|second_count|count_16:count_16_inst
clk => q[14]~reg0.CLK
clk => q[13]~reg0.CLK
clk => q[12]~reg0.CLK
clk => q[11]~reg0.CLK
clk => q[10]~reg0.CLK
clk => q[9]~reg0.CLK
clk => q[8]~reg0.CLK
clk => q[7]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[15]~reg0.CLK
reset => q[14]~reg0.ACLR
reset => q[13]~reg0.ACLR
reset => q[12]~reg0.ACLR
reset => q[11]~reg0.ACLR
reset => q[10]~reg0.ACLR
reset => q[9]~reg0.ACLR
reset => q[8]~reg0.ACLR
reset => q[7]~reg0.ACLR
reset => q[6]~reg0.ACLR
reset => q[5]~reg0.ACLR
reset => q[4]~reg0.ACLR
reset => q[3]~reg0.ACLR
reset => q[2]~reg0.ACLR
reset => q[1]~reg0.ACLR
reset => q[0]~reg0.ACLR
reset => q[15]~reg0.ACLR
enable => q~0.OUTPUTSELECT
enable => q~1.OUTPUTSELECT
enable => q~2.OUTPUTSELECT
enable => q~3.OUTPUTSELECT
enable => q~4.OUTPUTSELECT
enable => q~5.OUTPUTSELECT
enable => q~6.OUTPUTSELECT
enable => q~7.OUTPUTSELECT
enable => q~8.OUTPUTSELECT
enable => q~9.OUTPUTSELECT
enable => q~10.OUTPUTSELECT
enable => q~11.OUTPUTSELECT
enable => q~12.OUTPUTSELECT
enable => q~13.OUTPUTSELECT
enable => q~14.OUTPUTSELECT
enable => q~15.OUTPUTSELECT
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE