controller_snoop.v

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// Produced by /usr/class/ee272/bin/snoopgen from file controller.in

// Remember to run Verilog with -x if any variables are subscripted


// 2 Clock phases: phi1 phi2
// Input, Verilog: sync_s1, irsim: sync_s1
// Input, Verilog: self_test_s1, irsim: self_test_s1
// Input, Verilog: external_y_s1, irsim: external_y_s1, vector[1:0]
// Input, Verilog: decoded_column_s1, irsim: decoded_column_s1, vector[3:0]
// Input, Verilog: phi2, irsim: phi2
// Input, Verilog: phi1, irsim: phi1
// Output, Verilog: fail_s1, irsim: fail_s1, Stable phase 1
// Output, Verilog: data_valid_s1, irsim: data_valid_s1, Stable phase 1
// Output, Verilog: decoded_bit_s1, irsim: decoded_bit_s1, Stable phase 1
// Output, Verilog: orig_del_bit_s1, irsim: orig_del_bit_s1, Stable phase 1
// Output, Verilog: sel_initial_s1, irsim: sel_initial_s1, Stable phase 1
// Output, Verilog: y1_s1, irsim: y1_s1, Stable phase 1
// Output, Verilog: y2_s1, irsim: y2_s1, Stable phase 1


module snooper(
	phi1, phi2, y2_s1, y1_s1, 
	sel_initial_s1, orig_del_bit_s1, decoded_bit_s1, data_valid_s1, 
	fail_s1, decoded_column_s1, external_y_s1, self_test_s1, 
	sync_s1);

input phi1;
input phi2;
input y2_s1;
input y1_s1;
input sel_initial_s1;
input orig_del_bit_s1;
input decoded_bit_s1;
input data_valid_s1;
input fail_s1;
input [3:0] decoded_column_s1;
input [1:0] external_y_s1;
input self_test_s1;
input sync_s1;

initial
begin
	$rsim_init();
	$rsim_check_on();
end

// One always block per input

always @(sync_s1) $rsim_log_input(sync_s1, "sync_s1");
always @(self_test_s1) $rsim_log_input(self_test_s1, "self_test_s1");
always @(external_y_s1)
begin
	$rsim_log_input(external_y_s1[1], "external_y_s1[1]");
	$rsim_log_input(external_y_s1[0], "external_y_s1[0]");
end
always @(decoded_column_s1)
begin
	$rsim_log_input(decoded_column_s1[3], "decoded_column_s1[3]");
	$rsim_log_input(decoded_column_s1[2], "decoded_column_s1[2]");
	$rsim_log_input(decoded_column_s1[1], "decoded_column_s1[1]");
	$rsim_log_input(decoded_column_s1[0], "decoded_column_s1[0]");
end
always @(phi2) $rsim_log_input(phi2, "phi2");
always @(phi1) $rsim_log_input(phi1, "phi1");

// One always block per inout


// Let go of inouts


// Check stable signals

always @(phi1)
begin
	$rsim_log_output(fail_s1, "fail_s1");
	$rsim_log_output(data_valid_s1, "data_valid_s1");
	$rsim_log_output(decoded_bit_s1, "decoded_bit_s1");
	$rsim_log_output(orig_del_bit_s1, "orig_del_bit_s1");
	$rsim_log_output(sel_initial_s1, "sel_initial_s1");
	$rsim_log_output(y1_s1, "y1_s1");
	$rsim_log_output(y2_s1, "y2_s1");
end

always @(phi2)
begin
end


// Check valid signals

always @(negedge phi1)
begin
end

always @(negedge phi2)
begin
end


// Check qualified signals

always @(phi1)
begin
end

always @(phi2)
begin
end



endmodule