spusnoop.v

modelsim快速入门教程

// Produced by /usr/class/ee272/bin/snoopgen from file s.in

// Remember to run Verilog with -x if any variables are subscripted


// 2 Clock phases: phi1 phi2
// Input, Verilog: decisions_b_s1, irsim: decisions_b_s1, vector[3:0]
// Input, Verilog: decisions_s1, irsim: decisions_s1, vector[3:0]
// Input, Verilog: phi2_b, irsim: phi2_b
// Input, Verilog: phi2, irsim: phi2_bb
// Input, Verilog: phi1_b, irsim: phi1_b
// Input, Verilog: phi1, irsim: phi1_bb
// Output, Verilog: decoded_column_s1, irsim: decoded_column_s1, vector[3:0], Stable phase 1


module snooper(
	phi1, phi1_b, phi2, phi2_b, 
	decisions_s1, decisions_b_s1, decoded_column_s1);

input phi1;
input phi1_b;
input phi2;
input phi2_b;
input [3:0] decisions_s1;
input [3:0] decisions_b_s1;
input [3:0] decoded_column_s1;

initial
begin
	$rsim_init();
	$rsim_check_on();
end

// One always block per input

always @(decisions_b_s1)
begin
	$rsim_log_input(decisions_b_s1[3], "decisions_b_s1[3]");
	$rsim_log_input(decisions_b_s1[2], "decisions_b_s1[2]");
	$rsim_log_input(decisions_b_s1[1], "decisions_b_s1[1]");
	$rsim_log_input(decisions_b_s1[0], "decisions_b_s1[0]");
end
always @(decisions_s1)
begin
	$rsim_log_input(decisions_s1[3], "decisions_s1[3]");
	$rsim_log_input(decisions_s1[2], "decisions_s1[2]");
	$rsim_log_input(decisions_s1[1], "decisions_s1[1]");
	$rsim_log_input(decisions_s1[0], "decisions_s1[0]");
end
always @(phi2_b) $rsim_log_input(phi2_b, "phi2_b");
always @(phi2) $rsim_log_input(phi2, "phi2_bb");
always @(phi1_b) $rsim_log_input(phi1_b, "phi1_b");
always @(phi1) $rsim_log_input(phi1, "phi1_bb");

// One always block per inout


// Let go of inouts


// Check stable signals

always @(phi1)
begin
	$rsim_log_output(decoded_column_s1[3], "decoded_column_s1[3]");
	$rsim_log_output(decoded_column_s1[2], "decoded_column_s1[2]");
	$rsim_log_output(decoded_column_s1[1], "decoded_column_s1[1]");
	$rsim_log_output(decoded_column_s1[0], "decoded_column_s1[0]");
end

always @(phi2)
begin
end


// Check valid signals

always @(negedge phi1)
begin
end

always @(negedge phi2)
begin
end


// Check qualified signals

always @(phi1)
begin
end

always @(phi2)
begin
end



endmodule