de2_tv.hier_info

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|DE2_TV
OSC_27 => OSC_27~0.IN1
OSC_50 => OSC_50~0.IN2
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => KEY[0]~3.IN1
KEY[1] => KEY[1]~2.IN1
KEY[2] => KEY[2]~1.IN1
KEY[3] => KEY[3]~0.IN1
DRAM_DQ[0] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[1] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[2] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[3] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[4] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[5] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[6] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[7] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[8] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[9] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[10] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[11] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[12] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[13] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[14] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_DQ[15] <= avl_m_w:DUT.zs_dq_to_and_from_the_sdram_0
DRAM_ADDR[0] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[1] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[2] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[3] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[4] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[5] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[6] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[7] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[8] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[9] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[10] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_ADDR[11] <= avl_m_w:DUT.zs_addr_from_the_sdram_0
DRAM_LDQM <= avl_m_w:DUT.zs_dqm_from_the_sdram_0
DRAM_UDQM <= avl_m_w:DUT.zs_dqm_from_the_sdram_0
DRAM_WE_N <= avl_m_w:DUT.zs_we_n_from_the_sdram_0
DRAM_CAS_N <= avl_m_w:DUT.zs_cas_n_from_the_sdram_0
DRAM_RAS_N <= avl_m_w:DUT.zs_ras_n_from_the_sdram_0
DRAM_CS_N <= avl_m_w:DUT.zs_cs_n_from_the_sdram_0
DRAM_BA_0 <= avl_m_w:DUT.zs_ba_from_the_sdram_0
DRAM_BA_1 <= avl_m_w:DUT.zs_ba_from_the_sdram_0
DRAM_CLK <= <GND>
DRAM_CKE <= avl_m_w:DUT.zs_cke_from_the_sdram_0
I2C_DATA <= <UNC>
I2C_CLK <= <UNC>
TD_RESET <= avl_m_w:DUT.TD_RESET_from_the_de2_tv2_0
TD_DATA[0] => TD_DATA[0]~7.IN1
TD_DATA[1] => TD_DATA[1]~6.IN1
TD_DATA[2] => TD_DATA[2]~5.IN1
TD_DATA[3] => TD_DATA[3]~4.IN1
TD_DATA[4] => TD_DATA[4]~3.IN1
TD_DATA[5] => TD_DATA[5]~2.IN1
TD_DATA[6] => TD_DATA[6]~1.IN1
TD_DATA[7] => TD_DATA[7]~0.IN1
TD_HS => TD_HS~0.IN1
TD_VS => TD_VS~0.IN1
TCK => TCK~0.IN1
TCS => TCS~0.IN1
TDI => TDI~0.IN1
TDO <= avl_m_w:DUT.TDO_from_the_de2_tv2_0


|DE2_TV|SDRAM_PLL:PLL1
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|DE2_TV|SDRAM_PLL:PLL1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
clk[0] <= clk[0]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|DE2_TV|system_Reset:rst
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK
iCLK => Cont[11].CLK
iCLK => Cont[10].CLK
iCLK => Cont[9].CLK
iCLK => Cont[8].CLK
iCLK => Cont[7].CLK
iCLK => Cont[6].CLK
iCLK => Cont[5].CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oRESET~reg0.CLK
iCLK => Cont[15].CLK
oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TV|avl_m_w:DUT
clk => clk~0.IN11
reset_n => reset_n_sources~0.IN1
EXT_CLOCK_to_the_de2_tv2_0 => EXT_CLOCK_to_the_de2_tv2_0~0.IN1
I2C_SCLK_from_the_de2_tv2_0 <= de2_tv2_0:the_de2_tv2_0.I2C_SCLK
I2C_SDAT_to_and_from_the_de2_tv2_0 <= de2_tv2_0:the_de2_tv2_0.I2C_SDAT
KEY_to_the_de2_tv2_0[0] => KEY_to_the_de2_tv2_0[0]~3.IN1
KEY_to_the_de2_tv2_0[1] => KEY_to_the_de2_tv2_0[1]~2.IN1
KEY_to_the_de2_tv2_0[2] => KEY_to_the_de2_tv2_0[2]~1.IN1
KEY_to_the_de2_tv2_0[3] => KEY_to_the_de2_tv2_0[3]~0.IN1
OSC_27_to_the_de2_tv2_0 => OSC_27_to_the_de2_tv2_0~0.IN1
OSC_50_to_the_de2_tv2_0 => OSC_50_to_the_de2_tv2_0~0.IN1
TCK_to_the_de2_tv2_0 => TCK_to_the_de2_tv2_0~0.IN1
TCS_to_the_de2_tv2_0 => TCS_to_the_de2_tv2_0~0.IN1
TDI_to_the_de2_tv2_0 => TDI_to_the_de2_tv2_0~0.IN1
TDO_from_the_de2_tv2_0 <= de2_tv2_0:the_de2_tv2_0.TDO
TD_DATA_to_the_de2_tv2_0[0] => TD_DATA_to_the_de2_tv2_0[0]~7.IN1
TD_DATA_to_the_de2_tv2_0[1] => TD_DATA_to_the_de2_tv2_0[1]~6.IN1
TD_DATA_to_the_de2_tv2_0[2] => TD_DATA_to_the_de2_tv2_0[2]~5.IN1
TD_DATA_to_the_de2_tv2_0[3] => TD_DATA_to_the_de2_tv2_0[3]~4.IN1
TD_DATA_to_the_de2_tv2_0[4] => TD_DATA_to_the_de2_tv2_0[4]~3.IN1
TD_DATA_to_the_de2_tv2_0[5] => TD_DATA_to_the_de2_tv2_0[5]~2.IN1
TD_DATA_to_the_de2_tv2_0[6] => TD_DATA_to_the_de2_tv2_0[6]~1.IN1
TD_DATA_to_the_de2_tv2_0[7] => TD_DATA_to_the_de2_tv2_0[7]~0.IN1
TD_HS_to_the_de2_tv2_0 => TD_HS_to_the_de2_tv2_0~0.IN1
TD_RESET_from_the_de2_tv2_0 <= de2_tv2_0:the_de2_tv2_0.TD_RESET
TD_VS_to_the_de2_tv2_0 => TD_VS_to_the_de2_tv2_0~0.IN1
zs_addr_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[2] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[3] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[4] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[5] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[6] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[7] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[8] <= sdram_0:the_sdram_0.zs_addr