de2_tv.hier_info

来自「DE2_TV_m_write.rar是用来去处抖动的」· HIER_INFO 代码 · 共 928 行 · 第 1/5 页

zs_addr_from_the_sdram_0[9] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[10] <= sdram_0:the_sdram_0.zs_addr
zs_addr_from_the_sdram_0[11] <= sdram_0:the_sdram_0.zs_addr
zs_ba_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_ba
zs_ba_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_ba
zs_cas_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cas_n
zs_cke_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cke
zs_cs_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cs_n
zs_dq_to_and_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[2] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[3] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[4] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[5] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[6] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[7] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[8] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[9] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[10] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[11] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[12] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[13] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[14] <= sdram_0:the_sdram_0.zs_dq
zs_dq_to_and_from_the_sdram_0[15] <= sdram_0:the_sdram_0.zs_dq
zs_dqm_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_dqm
zs_dqm_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_dqm
zs_ras_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_ras_n
zs_we_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_we_n


|DE2_TV|avl_m_w:DUT|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
clk => cpu_0_jtag_debug_module_arb_share_counter[1].CLK
clk => cpu_0_jtag_debug_module_arb_share_counter[0].CLK
clk => cpu_0_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_0_jtag_debug_module_arb_addend[1].CLK
clk => cpu_0_jtag_debug_module_arb_addend[0].CLK
clk => d1_cpu_0_jtag_debug_module_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAB
cpu_0_data_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAB
cpu_0_data_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAB
cpu_0_data_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAB
cpu_0_data_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAB
cpu_0_data_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAB
cpu_0_data_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAB
cpu_0_data_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAB
cpu_0_data_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAB
cpu_0_data_master_address_to_slave[11] => Equal0.IN11
cpu_0_data_master_address_to_slave[12] => Equal0.IN10
cpu_0_data_master_address_to_slave[13] => Equal0.IN9
cpu_0_data_master_address_to_slave[14] => Equal0.IN8
cpu_0_data_master_address_to_slave[15] => Equal0.IN7
cpu_0_data_master_address_to_slave[16] => Equal0.IN6
cpu_0_data_master_address_to_slave[17] => Equal0.IN5
cpu_0_data_master_address_to_slave[18] => Equal0.IN4
cpu_0_data_master_address_to_slave[19] => Equal0.IN3
cpu_0_data_master_address_to_slave[20] => Equal0.IN2
cpu_0_data_master_address_to_slave[21] => Equal0.IN1
cpu_0_data_master_address_to_slave[22] => Equal0.IN0
cpu_0_data_master_address_to_slave[23] => Equal0.IN34
cpu_0_data_master_byteenable[0] => cpu_0_jtag_debug_module_byteenable~3.DATAB
cpu_0_data_master_byteenable[1] => cpu_0_jtag_debug_module_byteenable~2.DATAB
cpu_0_data_master_byteenable[2] => cpu_0_jtag_debug_module_byteenable~1.DATAB
cpu_0_data_master_byteenable[3] => cpu_0_jtag_debug_module_byteenable~0.DATAB
cpu_0_data_master_debugaccess => cpu_0_jtag_debug_module_debugaccess.DATAIN
cpu_0_data_master_read => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_data_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~0.IN0
cpu_0_data_master_write => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN1
cpu_0_data_master_write => cpu_0_jtag_debug_module_write~0.IN0
cpu_0_data_master_write => in_a_write_cycle.IN0
cpu_0_data_master_writedata[0] => cpu_0_jtag_debug_module_writedata[0].DATAIN
cpu_0_data_master_writedata[1] => cpu_0_jtag_debug_module_writedata[1].DATAIN
cpu_0_data_master_writedata[2] => cpu_0_jtag_debug_module_writedata[2].DATAIN
cpu_0_data_master_writedata[3] => cpu_0_jtag_debug_module_writedata[3].DATAIN
cpu_0_data_master_writedata[4] => cpu_0_jtag_debug_module_writedata[4].DATAIN
cpu_0_data_master_writedata[5] => cpu_0_jtag_debug_module_writedata[5].DATAIN
cpu_0_data_master_writedata[6] => cpu_0_jtag_debug_module_writedata[6].DATAIN
cpu_0_data_master_writedata[7] => cpu_0_jtag_debug_module_writedata[7].DATAIN
cpu_0_data_master_writedata[8] => cpu_0_jtag_debug_module_writedata[8].DATAIN
cpu_0_data_master_writedata[9] => cpu_0_jtag_debug_module_writedata[9].DATAIN
cpu_0_data_master_writedata[10] => cpu_0_jtag_debug_module_writedata[10].DATAIN
cpu_0_data_master_writedata[11] => cpu_0_jtag_debug_module_writedata[11].DATAIN
cpu_0_data_master_writedata[12] => cpu_0_jtag_debug_module_writedata[12].DATAIN
cpu_0_data_master_writedata[13] => cpu_0_jtag_debug_module_writedata[13].DATAIN
cpu_0_data_master_writedata[14] => cpu_0_jtag_debug_module_writedata[14].DATAIN
cpu_0_data_master_writedata[15] => cpu_0_jtag_debug_module_writedata[15].DATAIN
cpu_0_data_master_writedata[16] => cpu_0_jtag_debug_module_writedata[16].DATAIN
cpu_0_data_master_writedata[17] => cpu_0_jtag_debug_module_writedata[17].DATAIN
cpu_0_data_master_writedata[18] => cpu_0_jtag_debug_module_writedata[18].DATAIN
cpu_0_data_master_writedata[19] => cpu_0_jtag_debug_module_writedata[19].DATAIN
cpu_0_data_master_writedata[20] => cpu_0_jtag_debug_module_writedata[20].DATAIN
cpu_0_data_master_writedata[21] => cpu_0_jtag_debug_module_writedata[21].DATAIN
cpu_0_data_master_writedata[22] => cpu_0_jtag_debug_module_writedata[22].DATAIN
cpu_0_data_master_writedata[23] => cpu_0_jtag_debug_module_writedata[23].DATAIN
cpu_0_data_master_writedata[24] => cpu_0_jtag_debug_module_writedata[24].DATAIN
cpu_0_data_master_writedata[25] => cpu_0_jtag_debug_module_writedata[25].DATAIN
cpu_0_data_master_writedata[26] => cpu_0_jtag_debug_module_writedata[26].DATAIN
cpu_0_data_master_writedata[27] => cpu_0_jtag_debug_module_writedata[27].DATAIN
cpu_0_data_master_writedata[28] => cpu_0_jtag_debug_module_writedata[28].DATAIN
cpu_0_data_master_writedata[29] => cpu_0_jtag_debug_module_writedata[29].DATAIN
cpu_0_data_master_writedata[30] => cpu_0_jtag_debug_module_writedata[30].DATAIN
cpu_0_data_master_writedata[31] => cpu_0_jtag_debug_module_writedata[31].DATAIN
cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAA
cpu_0_instruction_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAA
cpu_0_instruction_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAA
cpu_0_instruction_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAA
cpu_0_instruction_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAA
cpu_0_instruction_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAA
cpu_0_instruction_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAA
cpu_0_instruction_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAA
cpu_0_instruction_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAA
cpu_0_instruction_master_address_to_slave[11] => Equal1.IN11
cpu_0_instruction_master_address_to_slave[12] => Equal1.IN10
cpu_0_instruction_master_address_to_slave[13] => Equal1.IN9
cpu_0_instruction_master_address_to_slave[14] => Equal1.IN8
cpu_0_instruction_master_address_to_slave[15] => Equal1.IN7
cpu_0_instruction_master_address_to_slave[16] => Equal1.IN6
cpu_0_instruction_master_address_to_slave[17] => Equal1.IN5
cpu_0_instruction_master_address_to_slave[18] => Equal1.IN4
cpu_0_instruction_master_address_to_slave[19] => Equal1.IN3
cpu_0_instruction_master_address_to_slave[20] => Equal1.IN2
cpu_0_instruction_master_address_to_slave[21] => Equal1.IN1
cpu_0_instruction_master_address_to_slave[22] => Equal1.IN0
cpu_0_instruction_master_address_to_slave[23] => Equal1.IN34
cpu_0_instruction_master_latency_counter => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~0.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~1.IN0
cpu_0_instruction_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~1.IN0
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~0.IN1
cpu_0_jtag_debug_module_readdata[0] => cpu_0_jtag_debug_module_readdata_from_sa[0].DATAIN
cpu_0_jtag_debug_module_readdata[1] => cpu_0_jtag_debug_module_readdata_from_sa[1].DATAIN
cpu_0_jtag_debug_module_readdata[2] => cpu_0_jtag_debug_module_readdata_from_sa[2].DATAIN
cpu_0_jtag_debug_module_readdata[3] => cpu_0_jtag_debug_module_readdata_from_sa[3].DATAIN
cpu_0_jtag_debug_module_readdata[4] => cpu_0_jtag_debug_module_readdata_from_sa[4].DATAIN
cpu_0_jtag_debug_module_readdata[5] => cpu_0_jtag_debug_module_readdata_from_sa[5].DATAIN
cpu_0_jtag_debug_module_readdata[6] => cpu_0_jtag_debug_module_readdata_from_sa[6].DATAIN
cpu_0_jtag_debug_module_readdata[7] => cpu_0_jtag_debug_module_readdata_from_sa[7].DATAIN
cpu_0_jtag_debug_module_readdata[8] => cpu_0_jtag_debug_module_readdata_from_sa[8].DATAIN
cpu_0_jtag_debug_module_readdata[9] => cpu_0_jtag_debug_module_readdata_from_sa[9].DATAIN
cpu_0_jtag_debug_module_readdata[10] => cpu_0_jtag_debug_module_readdata_from_sa[10].DATAIN
cpu_0_jtag_debug_module_readdata[11] => cpu_0_jtag_debug_module_readdata_from_sa[11].DATAIN
cpu_0_jtag_debug_module_readdata[12] => cpu_0_jtag_debug_module_readdata_from_sa[12].DATAIN
cpu_0_jtag_debug_module_readdata[13] => cpu_0_jtag_debug_module_readdata_from_sa[13].DATAIN
cpu_0_jtag_debug_module_readdata[14] => cpu_0_jtag_debug_module_readdata_from_sa[14].DATAIN
cpu_0_jtag_debug_module_readdata[15] => cpu_0_jtag_debug_module_readdata_from_sa[15].DATAIN
cpu_0_jtag_debug_module_readdata[16] => cpu_0_jtag_debug_module_readdata_from_sa[16].DATAIN
cpu_0_jtag_debug_module_readdata[17] => cpu_0_jtag_debug_module_readdata_from_sa[17].DATAIN
cpu_0_jtag_debug_module_readdata[18] => cpu_0_jtag_debug_module_readdata_from_sa[18].DATAIN
cpu_0_jtag_debug_module_readdata[19] => cpu_0_jtag_debug_module_readdata_from_sa[19].DATAIN
cpu_0_jtag_debug_module_readdata[20] => cpu_0_jtag_debug_module_readdata_from_sa[20].DATAIN
cpu_0_jtag_debug_module_readdata[21] => cpu_0_jtag_debug_module_readdata_from_sa[21].DATAIN
cpu_0_jtag_debug_module_readdata[22] => cpu_0_jtag_debug_module_readdata_from_sa[22].DATAIN
cpu_0_jtag_debug_module_readdata[23] => cpu_0_jtag_debug_module_readdata_from_sa[23].DATAIN
cpu_0_jtag_debug_module_readdata[24] => cpu_0_jtag_debug_module_readdata_from_sa[24].DATAIN
cpu_0_jtag_debug_module_readdata[25] => cpu_0_jtag_debug_module_readdata_from_sa[25].DATAIN
cpu_0_jtag_debug_module_readdata[26] => cpu_0_jtag_debug_module_readdata_from_sa[26].DATAIN
cpu_0_jtag_debug_module_readdata[27] => cpu_0_jtag_debug_module_readdata_from_sa[27].DATAIN
cpu_0_jtag_debug_module_readdata[28] => cpu_0_jtag_debug_module_readdata_from_sa[28].DATAIN
cpu_0_jtag_debug_module_readdata[29] => cpu_0_jtag_debug_module_readdata_from_sa[29].DATAIN
cpu_0_jtag_debug_module_readdata[30] => cpu_0_jtag_debug_module_readdata_from_sa[30].DATAIN
cpu_0_jtag_debug_module_readdata[31] => cpu_0_jtag_debug_module_readdata_from_sa[31].DATAIN
cpu_0_jtag_debug_module_resetrequest => cpu_0_jtag_debug_module_resetrequest_from_sa.DATAIN
reset_n => cpu_0_jtag_debug_module_reset_n.DATAIN
reset_n => d1_cpu_0_jtag_debug_module_end_xfer~reg0.PRESET
reset_n => cpu_0_jtag_debug_module_arb_share_counter[0].ACLR
reset_n => cpu_0_jtag_debug_module_arb_share_counter[1].ACLR
reset_n => cpu_0_jtag_debug_module_slavearbiterlockenable.ACLR
reset_n => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.ACLR
reset_n => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.ACLR
reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].ACLR
reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].ACLR
reset_n => cpu_0_jtag_debug_module_arb_addend[0].PRESET
reset_n => cpu_0_jtag_debug_module_arb_addend[1].ACLR
reset_n => d1_reasons_to_wait.ACLR
reset_n => cpu_0_jtag_debug_module_reset.DATAIN
cpu_0_data_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module <= cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE