📄 de2_tv.tan.rpt
字号:
; -2.383 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[11] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.004 ns ; 9.387 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[17] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[16] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[25] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[21] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[20] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.379 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[19] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.974 ns ; 9.353 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[5] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[3] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[2] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[1] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[4] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.378 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[0] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.972 ns ; 9.350 ns ;
; -2.369 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[11] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.004 ns ; 9.373 ns ;
; -2.366 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[9] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.367 ns ;
; -2.366 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[8] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.367 ns ;
; -2.366 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[7] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.367 ns ;
; -2.366 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[10] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.367 ns ;
; -2.366 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[6] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.367 ns ;
; -2.360 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[24] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.996 ns ; 9.356 ns ;
; -2.360 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[23] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.996 ns ; 9.356 ns ;
; -2.360 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[22] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.996 ns ; 9.356 ns ;
; -2.360 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[28] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.996 ns ; 9.356 ns ;
; -2.360 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.996 ns ; 9.356 ns ;
; -2.358 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[9] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.359 ns ;
; -2.358 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[8] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.359 ns ;
; -2.358 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[7] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.359 ns ;
; -2.358 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[10] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.359 ns ;
; -2.358 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[6] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 7.001 ns ; 9.359 ns ;
; -2.347 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[18] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.999 ns ; 9.346 ns ;
; -2.347 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[34] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.999 ns ; 9.346 ns ;
; -2.347 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[29] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.999 ns ; 9.346 ns ;
; -2.347 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[39] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.999 ns ; 9.346 ns ;
; -2.347 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[31] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.999 ns ; 9.346 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[7] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.991 ns ; 9.319 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[11] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.991 ns ; 9.319 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[9] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.991 ns ; 9.319 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[12] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.991 ns ; 9.319 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[10] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ; 6.991 ns ; 9.319 ns ;
; -2.328 ns ; None ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[8] ; OSC_50 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns ⌨️ 快捷键说明
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