de2_tv.tan.rpt

来自「DE2_TV_m_write.rar是用来去处抖动的」· RPT 代码 · 共 200 行 · 第 1/5 页

; -2.419 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[35]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.415 ns                ;
; -2.419 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[37]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.415 ns                ;
; -2.404 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[15]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.380 ns                ;
; -2.404 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[14]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.380 ns                ;
; -2.404 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[12]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.380 ns                ;
; -2.404 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[13]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.380 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[24]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[23]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[22]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[36]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[30]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[33]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[35]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[28]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[37]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.400 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[38]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.396 ns                ;
; -2.396 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[15]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.372 ns                ;
; -2.396 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[14]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.372 ns                ;
; -2.396 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[12]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.372 ns                ;
; -2.396 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[13]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.976 ns                  ; 9.372 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[18]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[34]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[29]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[39]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[32]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.395 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[31]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.999 ns                  ; 9.394 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[5]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[3]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[2]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[1]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[4]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.394 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[0]                                                                                 ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.972 ns                  ; 9.366 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[17]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[16]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[25]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[21]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[20]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.389 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[19]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.974 ns                  ; 9.363 ns                ;
; -2.386 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[32]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.984 ns                  ; 9.370 ns                ;
; -2.386 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[40]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.984 ns                  ; 9.370 ns                ;