de2_tv.tan.rpt

DE2_TV_m_write.rar是用来去处抖动的

; Analyze latches as synchronous elements               ; On                 ;                 ;                          ;                                       ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                          ;                                       ;
; Enable Clock Latency                                  ; Off                ;                 ;                          ;                                       ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                          ;                                       ;
; Number of destination nodes to report                 ; 10                 ;                 ;                          ;                                       ;
; Number of paths to report                             ; 200                ;                 ;                          ;                                       ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                          ;                                       ;
; Use Fast Timing Models                                ; Off                ;                 ;                          ;                                       ;
; Report IO Paths Separately                            ; Off                ;                 ;                          ;                                       ;
; Clock Settings                                        ; OSC_50             ;                 ; OSC_50                   ;                                       ;
; Maximum Delay                                         ; 100 ns             ;                 ; data_in_d1               ; avl_m_w_reset_clk_domain_synch_module ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe5|dffe6a  ; dcfifo_8ef1                           ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a ; dcfifo_8ef1                           ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+---------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                               ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                              ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; OSC_50   ; 2                     ; 1                   ; -2.784 ns ;              ;
; OSC_50                                       ; OSC_50             ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP                 ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; OSC_27                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; TD_HS                                        ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~UPDATEUSER              ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                            ; To                                                                                                                                                                                   ; From Clock                                   ; To Clock                                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; -2.697 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.985 ns                  ; 9.682 ns                ;
; -2.697 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[26]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.985 ns                  ; 9.682 ns                ;
; -2.419 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[36]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.415 ns                ;
; -2.419 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[30]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.415 ns                ;
; -2.419 ns                               ; None                                                ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_0[33]                                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 7.216 ns                    ; 6.996 ns                  ; 9.415 ns                ;