de2_tv.tan.rpt

DE2_TV_m_write.rar是用来去处抖动的

without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------------+------------+-----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Type                                                        ; Slack      ; Required Time                     ; Actual Time                                    ; From                                                                                           ; To                                                                                                                                                                   ; From Clock                                   ; To Clock                                     ; Failed Paths ;
+-------------------------------------------------------------+------------+-----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Worst-case tsu                                              ; N/A        ; None                              ; 8.835 ns                                       ; TD_DATA[4]                                                                                     ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|ITU_656_Decoder:u4|TV_Y[9]                                                                        ; --                                           ; OSC_27                                       ; 0            ;
; Worst-case tco                                              ; N/A        ; None                              ; 3.152 ns                                       ; avl_m_w:DUT|sdram_0:the_sdram_0|m_bank[0]                                                      ; DRAM_BA_0                                                                                                                                                            ; OSC_50                                       ; --                                           ; 0            ;
; Worst-case tpd                                              ; N/A        ; None                              ; 12.343 ns                                      ; KEY[0]                                                                                         ; TD_RESET                                                                                                                                                             ; --                                           ; --                                           ; 0            ;
; Worst-case th                                               ; N/A        ; None                              ; 2.699 ns                                       ; altera_internal_jtag~TMSUTAP                                                                   ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]                                                                                              ; --                                           ; altera_internal_jtag~TCKUTAP                 ; 0            ;
; Clock Setup: 'OSC_50'                                       ; -13.444 ns ; 50.00 MHz ( period = 20.000 ns )  ; N/A                                            ; avl_m_w:DUT|cpu_0:the_cpu_0|d_write                                                            ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[31]                                                                                                ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; OSC_50                                       ; 2770         ;
; Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1' ; -2.697 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write                                ; avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27]                                                                ; OSC_50                                       ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 1389         ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                 ; N/A        ; None                              ; 62.52 MHz ( period = 15.996 ns )               ; sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]                                ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                         ; altera_internal_jtag~TCKUTAP                 ; altera_internal_jtag~TCKUTAP                 ; 0            ;
; Clock Setup: 'OSC_27'                                       ; N/A        ; None                              ; 105.84 MHz ( period = 9.448 ns )               ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|oDVAL          ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|a_graycounter_l27:wrptr_gp|counter_ffa[10] ; OSC_27                                       ; OSC_27                                       ; 0            ;
; Clock Setup: 'TD_HS'                                        ; N/A        ; None                              ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|Stable_Cont[0] ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|Stable_Cont[7]                                                                       ; TD_HS                                        ; TD_HS                                        ; 0            ;
; Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'  ; 0.499 ns   ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; avl_m_w:DUT|sdram_0:the_sdram_0|i_cmd[3]                                                       ; avl_m_w:DUT|sdram_0:the_sdram_0|i_cmd[3]                                                                                                                             ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'OSC_50'                                        ; 0.499 ns   ; 50.00 MHz ( period = 20.000 ns )  ; N/A                                            ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0       ; avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0                                                                             ; OSC_50                                       ; OSC_50                                       ; 0            ;
; Total number of failed paths                                ;            ;                                   ;                                                ;                                                                                                ;                                                                                                                                                                      ;                                              ;                                              ; 4159         ;
+-------------------------------------------------------------+------------+-----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                        ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+---------------------------------------+
; Option                                                ; Setting            ; From            ; To                       ; Entity Name                           ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+---------------------------------------+
; Device Name                                           ; EP2C35F672C8       ;                 ;                          ;                                       ;
; Timing Models                                         ; Final              ;                 ;                          ;                                       ;
; Default hold multicycle                               ; Same as Multicycle ;                 ;                          ;                                       ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                          ;                                       ;
; Cut off read during write signal paths                ; On                 ;                 ;                          ;                                       ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                          ;                                       ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                          ;                                       ;
; Ignore Clock Settings                                 ; Off                ;                 ;                          ;                                       ;