📄 de2_tv.tan.rpt
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Classic Timing Analyzer report for DE2_TV
Sun Mar 30 21:02:43 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Web Edition
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
6. Clock Setup: 'OSC_50'
7. Clock Setup: 'altera_internal_jtag~TCKUTAP'
8. Clock Setup: 'OSC_27'
9. Clock Setup: 'TD_HS'
10. Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
11. Clock Hold: 'OSC_50'
12. tsu
13. tco
14. tpd
15. th
16. Ignored Timing Assignments
17. Timing Analyzer Messages
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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
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