de2_tv.fit.rpt

DE2_TV_m_write.rar是用来去处抖动的

; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                             ;
+---------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node                                                    ; Action          ; Operation        ; Reason                                 ; Node Port ; Destination Node                                                                                                                                                  ; Destination Port ;
+---------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[0]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[0]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[0]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[1]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[1]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[1]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[2]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[2]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[2]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[3]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[3]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[3]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[4]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[4]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[4]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[5]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[5]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[5]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[6]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[6]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[6]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[7]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[7]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[7]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[8]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[8]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[8]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[9]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[9]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[9]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[10]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[10]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[10]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[11]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[11]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[11]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[12]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[12]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[12]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[13]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[13]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[13]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[14]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[14]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[14]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[15]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[15]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[15]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[16]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[17]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[18]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[19]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[20]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[21]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[22]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[23]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[24]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[25]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[26]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[27]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[28]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[29]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;