de2_tv.fit.rpt

来自「DE2_TV_m_write.rar是用来去处抖动的」· RPT 代码 · 共 300 行 · 第 1/5 页

; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[30]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src1[31]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[0]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[0]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[0]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[0]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[1]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[1]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[1]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[1]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[2]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[2]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[2]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[2]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[3]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[3]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[3]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[3]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[4]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[4]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[4]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[4]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[5]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[5]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[5]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[5]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[6]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[6]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[6]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[6]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[7]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[7]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[7]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[7]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[8]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[8]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[8]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[8]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[9]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[9]               ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[9]~_Duplicate_1                                                                                                            ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[9]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[10]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[10]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[10]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[11]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[11]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[11]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[12]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[12]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[12]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[13]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[13]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[13]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[14]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[14]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[14]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[15]              ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[15]              ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[15]~_Duplicate_1                                                                                                           ; REGOUT           ;
; avl_m_w:DUT|cpu_0:the_cpu_0|A_mul_src2[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB            ;
; avl_m_w:DUT|cpu_0:the_cpu_0|D_bht_data[0]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_amh1:auto_generated|altsyncram_pfn1:altsyncram1|q_a[0]                ; PORTADATAOUT     ;
; avl_m_w:DUT|cpu_0:the_cpu_0|D_bht_data[1]               ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ; avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_amh1:auto_generated|altsyncram_pfn1:altsyncram1|q_a[1]                ; PORTADATAOUT     ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[0]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[0]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[1]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[1]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[2]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[2]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[3]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[3]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[4]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[4]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[5]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[5]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[6]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[6]                                                                                                                                                      ; DATAIN           ;
; avl_m_w:DUT|sdram_0:the_sdram_0|m_addr[7]               ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; DRAM_ADDR[7]                                                                                                                                                      ; DATAIN           ;