de2_tv.fit.rpt

DE2_TV_m_write.rar是用来去处抖动的

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Fitter Summary                                                              ;
+------------------------------------+----------------------------------------+
; Fitter Status                      ; Successful - Sun Mar 30 21:01:38 2008  ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Web Edition ;
; Revision Name                      ; DE2_TV                                 ;
; Top-level Entity Name              ; DE2_TV                                 ;
; Family                             ; Cyclone II                             ;
; Device                             ; EP2C35F672C8                           ;
; Timing Models                      ; Final                                  ;
; Total logic elements               ; 4,597 / 33,216 ( 14 % )                ;
;     Total combinational functions  ; 3,744 / 33,216 ( 11 % )                ;
;     Dedicated logic registers      ; 3,146 / 33,216 ( 9 % )                 ;
; Total registers                    ; 3214                                   ;
; Total pins                         ; 66 / 475 ( 14 % )                      ;
; Total virtual pins                 ; 0                                      ;
; Total memory bits                  ; 386,048 / 483,840 ( 80 % )             ;
; Embedded Multiplier 9-bit elements ; 22 / 70 ( 31 % )                       ;
; Total PLLs                         ; 1 / 4 ( 25 % )                         ;
+------------------------------------+----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C35F672C8                   ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;