rsdecoder.v

来自「reed-solomon译码器。共有7个文件」· Verilog 代码 · 共 56 行

module RSDecoder(recword, start, clock1, clock2, reset, ready,
               errfound, decode_fail, dataoutstart, dataoutend,
               corr_recword);

input [4:0] recword;
input clock1, clock2;
input start, reset;
output ready, decode_fail, errfound, dataoutstart, dataoutend;
output [4:0] corr_recword;

wire active_SYN, active_BM, active_CHIEN, en_SYNcell;
wire evalsynd, holdsynd, evalerror, lastdataout;
wire shift_fifo, hold_fifo, en_infifo, en_outfifo;
wire errdetect, finish_BM;
wire [4:0] dataout_fifo, errorvalue;

wire [4:0] syndvalue0, syndvalue1, syndvalue2, syndvalue3, 
           syndvalue4, syndvalue5, syndvalue6, syndvalue7, 
           syndvalue8, syndvalue9, syndvalue10, syndvalue11;
wire [4:0] lambda0, lambda1, lambda2, lambda3, lambda4, lambda5, 
           lambda6;
wire [4:0] homega0, homega1, homega2, homega3, homega4, homega5;
wire [2:0] rootcntr, lambda_degree;

assign en_SYNcell = shift_fifo;

SYNblock SYNblock(recword, clock1, clock2, active_SYN, reset, syndvalue0,
               syndvalue1, syndvalue2, syndvalue3, syndvalue4, 
               syndvalue5, syndvalue6, syndvalue7, syndvalue8, 
               syndvalue9, syndvalue10, syndvalue11, errdetect, 
               en_SYNcell, evalsynd, holdsynd);
BM_block BMblock(active_BM, clock1, clock2, reset, syndvalue0, syndvalue1,                 syndvalue2, syndvalue3, syndvalue4, syndvalue5, syndvalue6, 
                syndvalue7, syndvalue8, syndvalue9, syndvalue10, syndvalue11, 
                lambda0, lambda1, lambda2, lambda3, lambda4, lambda5, 
                lambda6, homega0, homega1, homega2, homega3, homega4, 
                homega5, lambda_degree, finish_BM);
CHIENblock CHIENblock(lambda0, lambda1, lambda2, lambda3, lambda4,
                  lambda5, lambda6, homega0, homega1, homega2,
                  homega3, homega4, homega5, errorvalue, clock1,
                  clock2, active_CHIEN, reset, lastdataout, evalerror,
                  en_outfifo, rootcntr);
MainControl controller(start, reset, clock1, clock2, finish_BM,
                  errdetect, rootcntr, lambda_degree, active_SYN, 
                  active_BM, active_CHIEN, evalsynd, holdsynd, 
                  errfound, decode_fail, ready, dataoutstart, dataoutend, 
                  shift_fifo, hold_fifo, en_infifo, en_outfifo, 
                  lastdataout, evalerror);
fifo_register fiforeg(clock1, clock2, shift_fifo, hold_fifo, 
                     en_outfifo, en_infifo, recword, dataout_fifo);

gfadder adder(errorvalue, dataout_fifo, corr_recword);                                  

endmodule