c7.vhd

来自「基于FPGA的多功能电子时钟的设计很经典的哦」· VHDL 代码 · 共 24 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity c7 is
    Port ( clk : in std_logic;
          dout : out std_logic_vector(3 downto 0));
end c7;
architecture Behavioral of c7 is
   signal count : std_logic_vector(3 downto 0);
begin
	process(clk)
	begin
	   if rising_edge(clk) then
		   if count = "0110" then
			   count <= "0000";
           else 
			   count <= count+1;
           end if;
      end if;
    dout <= count;
    end process;
end Behavioral;