clk_div.vhd

来自「基于FPGA的多功能电子时钟的设计很经典的哦」· VHDL 代码 · 共 50 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(clk:in std_logic;
	clk1:out std_logic;
	clk16:out std_logic;
	clk512:out std_logic);
end;
architecture one of clk_div is
signal clk1_1:std_logic;
signal clk2_2:std_logic;
signal clk3_3:std_logic;
begin
process(clk)
variable count:integer range 0 to 511;-----1Hz
begin
if clk'event and clk='1'then
	if count=511 then
		clk1_1<=not clk1_1;
		count:=0;
	else
		count:=count+1;
		end if;
end if;
end process;
-------------------------------
process(clk)
variable count:integer range 0 to 31;------16Hz
begin
if clk'event and clk='1'then
	if count=31 then
		clk2_2<=not clk2_2;
		count:=0;
	else
		count:=count+1;
		end if;
end if;
end process;
-----------------------------------
process(clk)
begin
if clk'event and clk='1'
then clk3_3<=not clk3_3;
end if;
end process;
clk1<=clk1_1;
clk16<=clk2_2;
clk512<=clk3_3;
end;