prev_cmp_block.qmsg

基于FPGA的多功能电子时钟的设计很经典的哦

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Allocated 164 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 16 16:46:55 2008 " "Info: Processing ended: Mon Jun 16 16:46:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 16 16:46:57 2008 " "Info: Processing started: Mon Jun 16 16:46:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Block -c Block " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Block -c Block" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 16 16:46:59 2008 " "Info: Processing ended: Mon Jun 16 16:46:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 16 16:47:00 2008 " "Info: Processing started: Mon Jun 16 16:47:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Block -c Block " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Block -c Block" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 992 1504 1672 1008 "CLK" "" } { 1240 1730 1768 1260 "CLK" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK2 " "Info: Assuming node \"CLK2\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 432 360 528 448 "CLK2" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK4 " "Info: Assuming node \"CLK4\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 704 360 528 720 "CLK4" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK4" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node \"CLK1\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 288 360 528 304 "CLK1" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK3 " "Info: Assuming node \"CLK3\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 568 360 528 584 "CLK3" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK6 " "Info: Assuming node \"CLK6\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1104 360 528 1120 "CLK6" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK6" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK5 " "Info: Assuming node \"CLK5\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 840 360 528 856 "CLK5" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK5" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst22\|clk2_2 " "Info: Detected ripple clock \"clk_div:inst22\|clk2_2\" as buffer" {  } { { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 31 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst22\|clk2_2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "counter6:inst3\|c " "Info: Detected ripple clock \"counter6:inst3\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 9 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:inst3\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "counter24:inst5\|c " "Info: Detected ripple clock \"counter24:inst5\|c\" as buffer" {  } { { "counter24.vhd" "" { Text "F:/FPGA/newszz/counter24.vhd" 9 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter24:inst5\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "counter6:inst1\|c " "Info: Detected ripple clock \"counter6:inst1\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 9 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:inst1\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:inst2\|c " "Info: Detected ripple clock \"counter10:inst2\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 9 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:inst2\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst22\|clk1_1 " "Info: Detected ripple clock \"clk_div:inst22\|clk1_1\" as buffer" {  } { { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 18 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst22\|clk1_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:inst\|c " "Info: Detected ripple clock \"counter10:inst\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 9 -1 0 } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:inst\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register zhongbai:inst30\|q1\[0\] register zhongbai:inst30\|q1\[6\] 104.17 MHz 9.6 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 104.17 MHz between source register \"zhongbai:inst30\|q1\[0\]\" and destination register \"zhongbai:inst30\|q1\[6\]\" (period= 9.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.800 ns + Longest register register " "Info: + Longest register to register delay is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zhongbai:inst30\|q1\[0\] 1 REG LC4_A46 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A46; Fanout = 4; REG Node = 'zhongbai:inst30\|q1\[0\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { zhongbai:inst30|q1[0] } "NODE_NAME" } } { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns zhongbai:inst30\|Equal0~77 2 COMB LC1_A46 1 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC1_A46; Fanout = 1; COMB Node = 'zhongbai:inst30\|Equal0~77'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { zhongbai:inst30|q1[0] zhongbai:inst30|Equal0~77 } "NODE_NAME" } } { "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 3.600 ns zhongbai:inst30\|Equal0~74 3 COMB LC2_A46 5 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 3.600 ns; Loc. = LC2_A46; Fanout = 5; COMB Node = 'zhongbai:inst30\|Equal0~74'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { zhongbai:inst30|Equal0~77 zhongbai:inst30|Equal0~74 } "NODE_NAME" } } { "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.800 ns zhongbai:inst30\|q1~831 4 COMB LC8_A46 6 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 5.800 ns; Loc. = LC8_A46; Fanout = 6; COMB Node = 'zhongbai:inst30\|q1~831'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { zhongbai:inst30|Equal0~74 zhongbai:inst30|q1~831 } "NODE_NAME" } } { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 7.800 ns zhongbai:inst30\|q1\[6\] 5 REG LC4_A47 4 " "Info: 5: + IC(1.000 ns) + CELL(1.000 ns) = 7.800 ns; Loc. = LC4_A47; Fanout = 4; REG Node = 'zhongbai:inst30\|q1\[6\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { zhongbai:inst30|q1~831 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns ( 82.05 % ) " "Info: Total cell delay = 6.400 ns ( 82.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 17.95 % ) " "Info: Total interconnect delay = 1.400 ns ( 17.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { zhongbai:inst30|q1[0] zhongbai:inst30|Equal0~77 zhongbai:inst30|Equal0~74 zhongbai:inst30|q1~831 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "7.800 ns" { zhongbai:inst30|q1[0] {} zhongbai:inst30|Equal0~77 {} zhongbai:inst30|Equal0~74 {} zhongbai:inst30|q1~831 {} zhongbai:inst30|q1[6] {} } { 0.000ns 0.200ns 0.000ns 0.200ns 1.000ns } { 0.000ns 1.500ns 1.900ns 2.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.800 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_78 19 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 992 1504 1672 1008 "CLK" "" } { 1240 1730 1768 1260 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk_div:inst22\|clk2_2 2 REG LC1_F11 13 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_F11; Fanout = 13; REG Node = 'clk_div:inst22\|clk2_2'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK clk_div:inst22|clk2_2 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 5.800 ns zhongbai:inst30\|q1\[6\] 3 REG LC4_A47 4 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC4_A47; Fanout = 4; REG Node = 'zhongbai:inst30\|q1\[6\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { clk_div:inst22|clk2_2 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 27.59 % ) " "Info: Total cell delay = 1.600 ns ( 27.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 72.41 % ) " "Info: Total interconnect delay = 4.200 ns ( 72.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[6] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.800 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_78 19 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 992 1504 1672 1008 "CLK" "" } { 1240 1730 1768 1260 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk_div:inst22\|clk2_2 2 REG LC1_F11 13 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_F11; Fanout = 13; REG Node = 'clk_div:inst22\|clk2_2'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK clk_div:inst22|clk2_2 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 5.800 ns zhongbai:inst30\|q1\[0\] 3 REG LC4_A46 4 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC4_A46; Fanout = 4; REG Node = 'zhongbai:inst30\|q1\[0\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { clk_div:inst22|clk2_2 zhongbai:inst30|q1[0] } "NODE_NAME" } } { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 27.59 % ) " "Info: Total cell delay = 1.600 ns ( 27.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 72.41 % ) " "Info: Total interconnect delay = 4.200 ns ( 72.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[0] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[6] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[0] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { zhongbai:inst30|q1[0] zhongbai:inst30|Equal0~77 zhongbai:inst30|Equal0~74 zhongbai:inst30|q1~831 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "7.800 ns" { zhongbai:inst30|q1[0] {} zhongbai:inst30|Equal0~77 {} zhongbai:inst30|Equal0~74 {} zhongbai:inst30|q1~831 {} zhongbai:inst30|q1[6] {} } { 0.000ns 0.200ns 0.000ns 0.200ns 1.000ns } { 0.000ns 1.500ns 1.900ns 2.000ns 1.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[6] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[6] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { CLK clk_div:inst22|clk2_2 zhongbai:inst30|q1[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { CLK {} CLK~out {} clk_div:inst22|clk2_2 {} zhongbai:inst30|q1[0] {} } { 0.000ns 0.000ns 1.400ns 2.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK2 register register c6:inst41\|count\[0\] c6:inst41\|count\[2\] 200.0 MHz Internal " "Info: Clock \"CLK2\" Internal fmax is restricted to 200.0 MHz between source register \"c6:inst41\|count\[0\]\" and destination register \"c6:inst41\|count\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest register register " "Info: + Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c6:inst41\|count\[0\] 1 REG LC4_A35 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A35; Fanout = 5; REG Node = 'c6:inst41\|count\[0\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c6:inst41|count[0] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns c6:inst41\|count\[2\] 2 REG LC7_A35 4 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC7_A35; Fanout = 4; REG Node = 'c6:inst41\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c6:inst41|count[0] c6:inst41|count[2] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 88.24 % ) " "Info: Total cell delay = 1.500 ns ( 88