block.map.qmsg

基于FPGA的多功能电子时钟的设计很经典的哦

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count counter6.vhd(29) " "Warning (10492): VHDL Process Statement warning at counter6.vhd(29): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "c6.vhd 2 1 " "Warning: Using design file c6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 c6-Behavioral " "Info: Found design unit 1: c6-Behavioral" {  } { { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 c6 " "Info: Found entity 1: c6" {  } { { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "c6 c6:inst41 " "Info: Elaborating entity \"c6\" for hierarchy \"c6:inst41\"" {  } { { "Block.bdf" "inst41" { Schematic "F:/FPGA/newszz/Block.bdf" { { 408 544 656 504 "inst41" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count c6.vhd(20) " "Warning (10492): VHDL Process Statement warning at c6.vhd(20): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter24.vhd 2 1 " "Warning: Using design file counter24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-Behavioral " "Info: Found design unit 1: counter24-Behavioral" {  } { { "counter24.vhd" "" { Text "F:/FPGA/newszz/counter24.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "F:/FPGA/newszz/counter24.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:inst5 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:inst5\"" {  } { { "Block.bdf" "inst5" { Schematic "F:/FPGA/newszz/Block.bdf" { { 760 704 848 856 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din counter24.vhd(17) " "Warning (10492): VHDL Process Statement warning at counter24.vhd(17): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter24.vhd" "" { Text "F:/FPGA/newszz/counter24.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count counter24.vhd(33) " "Warning (10492): VHDL Process Statement warning at counter24.vhd(33): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter24.vhd" "" { Text "F:/FPGA/newszz/counter24.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "c24.vhd 2 1 " "Warning: Using design file c24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 c24-Behavioral " "Info: Found design unit 1: c24-Behavioral" {  } { { "c24.vhd" "" { Text "F:/FPGA/newszz/c24.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 c24 " "Info: Found entity 1: c24" {  } { { "c24.vhd" "" { Text "F:/FPGA/newszz/c24.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "c24 c24:inst4 " "Info: Elaborating entity \"c24\" for hierarchy \"c24:inst4\"" {  } { { "Block.bdf" "inst4" { Schematic "F:/FPGA/newszz/Block.bdf" { { 816 544 656 912 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count c24.vhd(24) " "Warning (10492): VHDL Process Statement warning at c24.vhd(24): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "c24.vhd" "" { Text "F:/FPGA/newszz/c24.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "decoder7.vhd 2 1 " "Warning: Using design file decoder7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder7-Behavioral " "Info: Found design unit 1: decoder7-Behavioral" {  } { { "decoder7.vhd" "" { Text "F:/FPGA/newszz/decoder7.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder7 " "Info: Found entity 1: decoder7" {  } { { "decoder7.vhd" "" { Text "F:/FPGA/newszz/decoder7.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder7 decoder7:inst13 " "Info: Elaborating entity \"decoder7\" for hierarchy \"decoder7:inst13\"" {  } { { "Block.bdf" "inst13" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1024 992 1136 1120 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter7.vhd 2 1 " "Warning: Using design file counter7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter7-Behavioral " "Info: Found design unit 1: counter7-Behavioral" {  } { { "counter7.vhd" "" { Text "F:/FPGA/newszz/counter7.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter7 " "Info: Found entity 1: counter7" {  } { { "counter7.vhd" "" { Text "F:/FPGA/newszz/counter7.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter7 counter7:inst6 " "Info: Elaborating entity \"counter7\" for hierarchy \"counter7:inst6\"" {  } { { "Block.bdf" "inst6" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1024 704 848 1120 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din counter7.vhd(17) " "Warning (10492): VHDL Process Statement warning at counter7.vhd(17): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter7.vhd" "" { Text "F:/FPGA/newszz/counter7.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count counter7.vhd(25) " "Warning (10492): VHDL Process Statement warning at counter7.vhd(25): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter7.vhd" "" { Text "F:/FPGA/newszz/counter7.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "c7.vhd 2 1 " "Warning: Using design file c7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 c7-Behavioral " "Info: Found design unit 1: c7-Behavioral" {  } { { "c7.vhd" "" { Text "F:/FPGA/newszz/c7.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 c7 " "Info: Found entity 1: c7" {  } { { "c7.vhd" "" { Text "F:/FPGA/newszz/c7.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "c7 c7:inst46 " "Info: Elaborating entity \"c7\" for hierarchy \"c7:inst46\"" {  } { { "Block.bdf" "inst46" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1080 544 656 1176 "inst46" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count c7.vhd(20) " "Warning (10492): VHDL Process Statement warning at c7.vhd(20): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "c7.vhd" "" { Text "F:/FPGA/newszz/c7.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "zhongbai.vhd 2 1 " "Warning: Using design file zhongbai.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zhongbai-one " "Info: Found design unit 1: zhongbai-one" {  } { { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 zhongbai " "Info: Found entity 1: zhongbai" {  } { { "zhongbai.vhd" "" { Text "F:/FPGA/newszz/zhongbai.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zhongbai zhongbai:inst30 " "Info: Elaborating entity \"zhongbai\" for hierarchy \"zhongbai:inst30\"" {  } { { "Block.bdf" "inst30" { Schematic "F:/FPGA/newszz/Block.bdf" { { 192 1760 1856 288 "inst30" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "c24:inst4\|count\[6\] data_in GND " "Warning (14130): Reduced register \"c24:inst4\|count\[6\]\" with stuck data_in port to stuck value GND" {  } { { "c24.vhd" "" { Text "F:/FPGA/newszz/c24.vhd" 13 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}