block.map.qmsg

基于FPGA的多功能电子时钟的设计很经典的哦

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 16 16:48:16 2008 " "Info: Processing started: Mon Jun 16 16:48:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Block -c Block " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Block -c Block" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block " "Info: Found entity 1: Block" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_div-one " "Info: Found design unit 1: clk_div-one" {  } { { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.vhd" "" { Text "F:/FPGA/newszz/clk_div.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "class.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file class.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 class-one " "Info: Found design unit 1: class-one" {  } { { "class.vhd" "" { Text "F:/FPGA/newszz/class.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 class " "Info: Found entity 1: class" {  } { { "class.vhd" "" { Text "F:/FPGA/newszz/class.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block " "Info: Elaborating entity \"Block\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "class class:inst27 " "Info: Elaborating entity \"class\" for hierarchy \"class:inst27\"" {  } { { "Block.bdf" "inst27" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1192 1584 1680 1288 "inst27" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b class.vhd(9) " "Warning (10631): VHDL Process Statement warning at class.vhd(9): inferring latch(es) for signal or variable \"b\", which holds its previous value in one or more paths through the process" {  } { { "class.vhd" "" { Text "F:/FPGA/newszz/class.vhd" 9 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b class.vhd(9) " "Info (10041): Inferred latch for \"b\" at class.vhd(9)" {  } { { "class.vhd" "" { Text "F:/FPGA/newszz/class.vhd" 9 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "decoder.vhd 2 1 " "Warning: Using design file decoder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-Behavioral " "Info: Found design unit 1: decoder-Behavioral" {  } { { "decoder.vhd" "" { Text "F:/FPGA/newszz/decoder.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "F:/FPGA/newszz/decoder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:inst7 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:inst7\"" {  } { { "Block.bdf" "inst7" { Schematic "F:/FPGA/newszz/Block.bdf" { { 208 992 1136 304 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter10.vhd 2 1 " "Warning: Using design file counter10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter10-Behavioral " "Info: Found design unit 1: counter10-Behavioral" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter10 " "Info: Found entity 1: counter10" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter10 counter10:inst " "Info: Elaborating entity \"counter10\" for hierarchy \"counter10:inst\"" {  } { { "Block.bdf" "inst" { Schematic "F:/FPGA/newszz/Block.bdf" { { 208 704 848 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din counter10.vhd(17) " "Warning (10492): VHDL Process Statement warning at counter10.vhd(17): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count counter10.vhd(28) " "Warning (10492): VHDL Process Statement warning at counter10.vhd(28): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter10.vhd" "" { Text "F:/FPGA/newszz/counter10.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:inst22 " "Info: Elaborating entity \"clk_div\" for hierarchy \"clk_div:inst22\"" {  } { { "Block.bdf" "inst22" { Schematic "F:/FPGA/newszz/Block.bdf" { { 968 1704 1800 1064 "inst22" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "c10.vhd 2 1 " "Warning: Using design file c10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 c10-Behavioral " "Info: Found design unit 1: c10-Behavioral" {  } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 c10 " "Info: Found entity 1: c10" {  } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "c10 c10:inst40 " "Info: Elaborating entity \"c10\" for hierarchy \"c10:inst40\"" {  } { { "Block.bdf" "inst40" { Schematic "F:/FPGA/newszz/Block.bdf" { { 264 544 656 360 "inst40" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count c10.vhd(20) " "Warning (10492): VHDL Process Statement warning at c10.vhd(20): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter6.vhd 2 1 " "Warning: Using design file counter6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter6-Behavioral " "Info: Found design unit 1: counter6-Behavioral" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter6 " "Info: Found entity 1: counter6" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter6 counter6:inst1 " "Info: Elaborating entity \"counter6\" for hierarchy \"counter6:inst1\"" {  } { { "Block.bdf" "inst1" { Schematic "F:/FPGA/newszz/Block.bdf" { { 352 704 848 448 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din counter6.vhd(18) " "Warning (10492): VHDL Process Statement warning at counter6.vhd(18): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter6.vhd" "" { Text "F:/FPGA/newszz/counter6.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}