prev_cmp_block.tan.qmsg

基于FPGA的多功能电子时钟的设计很经典的哦

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK6 register register c7:inst46\|count\[1\] c7:inst46\|count\[2\] 200.0 MHz Internal " "Info: Clock \"CLK6\" Internal fmax is restricted to 200.0 MHz between source register \"c7:inst46\|count\[1\]\" and destination register \"c7:inst46\|count\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest register register " "Info: + Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c7:inst46\|count\[1\] 1 REG LC3_C12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C12; Fanout = 5; REG Node = 'c7:inst46\|count\[1\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c7:inst46|count[1] } "NODE_NAME" } } { "c7.vhd" "" { Text "F:/FPGA/newszz/c7.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns c7:inst46\|count\[2\] 2 REG LC4_C12 5 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC4_C12; Fanout = 5; REG Node = 'c7:inst46\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c7:inst46|count[1] c7:inst46|count[2] } "NODE_NAME" } } { "c7.vhd" "" { Text "F:/FPGA/newszz/c7.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 88.24 % ) " "Info: Total cell delay = 1.500 ns ( 88.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 11.76 % ) " "Info: Total interconnect delay = 0.200 ns ( 11.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c7:inst46|count[1] c7:inst46|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c7:inst46|count[1] {} c7:inst46|count[2] {} } { 0.000ns 0.200ns } { 0.000ns 1.50