📄 prev_cmp_block.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK4 register register c6:inst43\|count\[0\] c6:inst43\|count\[2\] 200.0 MHz Internal " "Info: Clock \"CLK4\" Internal fmax is restricted to 200.0 MHz between source register \"c6:inst43\|count\[0\]\" and destination register \"c6:inst43\|count\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest register register " "Info: + Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c6:inst43\|count\[0\] 1 REG LC3_G14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_G14; Fanout = 5; REG Node = 'c6:inst43\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c6:inst43|count[0] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns c6:inst43\|count\[2\] 2 REG LC4_G14 4 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC4_G14; Fanout = 4; REG Node = 'c6:inst43\|count\[2\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c6:inst43|count[0] c6:inst43|count[2] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 88.24 % ) " "Info: Total cell delay = 1.500 ns ( 88.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 11.76 % ) " "Info: Total interconnect delay = 0.200 ns ( 11.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c6:inst43|count[0] c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c6:inst43|count[0] {} c6:inst43|count[2] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK4 destination 9.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK4\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK4 1 CLK PIN_11 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_11; Fanout = 4; CLK Node = 'CLK4'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK4 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 704 360 528 720 "CLK4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.100 ns) + CELL(0.000 ns) 9.500 ns c6:inst43\|count\[2\] 2 REG LC4_G14 4 " "Info: 2: + IC(6.100 ns) + CELL(0.000 ns) = 9.500 ns; Loc. = LC4_G14; Fanout = 4; REG Node = 'c6:inst43\|count\[2\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK4 c6:inst43|count[2] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 35.79 % ) " "Info: Total cell delay = 3.400 ns ( 35.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 64.21 % ) " "Info: Total interconnect delay = 6.100 ns ( 64.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[2] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK4 source 9.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK4\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK4 1 CLK PIN_11 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_11; Fanout = 4; CLK Node = 'CLK4'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK4 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 704 360 528 720 "CLK4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.100 ns) + CELL(0.000 ns) 9.500 ns c6:inst43\|count\[0\] 2 REG LC3_G14 5 " "Info: 2: + IC(6.100 ns) + CELL(0.000 ns) = 9.500 ns; Loc. = LC3_G14; Fanout = 5; REG Node = 'c6:inst43\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK4 c6:inst43|count[0] } "NODE_NAME" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 35.79 % ) " "Info: Total cell delay = 3.400 ns ( 35.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 64.21 % ) " "Info: Total interconnect delay = 6.100 ns ( 64.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[0] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[2] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[0] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c6:inst43|count[0] c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c6:inst43|count[0] {} c6:inst43|count[2] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[2] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK4 c6:inst43|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK4 {} CLK4~out {} c6:inst43|count[0] {} } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c6:inst43|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c6:inst43|count[2] {} } { } { } "" } } { "c6.vhd" "" { Text "F:/FPGA/newszz/c6.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK1 register register c10:inst40\|count\[0\] c10:inst40\|count\[3\] 200.0 MHz Internal " "Info: Clock \"CLK1\" Internal fmax is restricted to 200.0 MHz between source register \"c10:inst40\|count\[0\]\" and destination register \"c10:inst40\|count\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest register register " "Info: + Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c10:inst40\|count\[0\] 1 REG LC5_H7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H7; Fanout = 5; REG Node = 'c10:inst40\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c10:inst40|count[0] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns c10:inst40\|count\[3\] 2 REG LC7_H7 3 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC7_H7; Fanout = 3; REG Node = 'c10:inst40\|count\[3\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst40|count[0] c10:inst40|count[3] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 88.24 % ) " "Info: Total cell delay = 1.500 ns ( 88.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 11.76 % ) " "Info: Total interconnect delay = 0.200 ns ( 11.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst40|count[0] c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c10:inst40|count[0] {} c10:inst40|count[3] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 9.800 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK1 1 CLK PIN_7 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_7; Fanout = 4; CLK Node = 'CLK1'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 288 360 528 304 "CLK1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.400 ns) + CELL(0.000 ns) 9.800 ns c10:inst40\|count\[3\] 2 REG LC7_H7 3 " "Info: 2: + IC(6.400 ns) + CELL(0.000 ns) = 9.800 ns; Loc. = LC7_H7; Fanout = 3; REG Node = 'c10:inst40\|count\[3\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.400 ns" { CLK1 c10:inst40|count[3] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 34.69 % ) " "Info: Total cell delay = 3.400 ns ( 34.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 65.31 % ) " "Info: Total interconnect delay = 6.400 ns ( 65.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[3] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 9.800 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK1 1 CLK PIN_7 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_7; Fanout = 4; CLK Node = 'CLK1'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 288 360 528 304 "CLK1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.400 ns) + CELL(0.000 ns) 9.800 ns c10:inst40\|count\[0\] 2 REG LC5_H7 5 " "Info: 2: + IC(6.400 ns) + CELL(0.000 ns) = 9.800 ns; Loc. = LC5_H7; Fanout = 5; REG Node = 'c10:inst40\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.400 ns" { CLK1 c10:inst40|count[0] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 34.69 % ) " "Info: Total cell delay = 3.400 ns ( 34.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 65.31 % ) " "Info: Total interconnect delay = 6.400 ns ( 65.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[0] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[3] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[0] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst40|count[0] c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c10:inst40|count[0] {} c10:inst40|count[3] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[3] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK1 c10:inst40|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK1 {} CLK1~out {} c10:inst40|count[0] {} } { 0.000ns 0.000ns 6.400ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c10:inst40|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c10:inst40|count[3] {} } { } { } "" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK3 register register c10:inst42\|count\[0\] c10:inst42\|count\[3\] 200.0 MHz Internal " "Info: Clock \"CLK3\" Internal fmax is restricted to 200.0 MHz between source register \"c10:inst42\|count\[0\]\" and destination register \"c10:inst42\|count\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest register register " "Info: + Longest register to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c10:inst42\|count\[0\] 1 REG LC6_A21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A21; Fanout = 5; REG Node = 'c10:inst42\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c10:inst42|count[0] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 1.700 ns c10:inst42\|count\[3\] 2 REG LC7_A21 3 " "Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'c10:inst42\|count\[3\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst42|count[0] c10:inst42|count[3] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 88.24 % ) " "Info: Total cell delay = 1.500 ns ( 88.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 11.76 % ) " "Info: Total interconnect delay = 0.200 ns ( 11.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst42|count[0] c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c10:inst42|count[0] {} c10:inst42|count[3] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK3 destination 6.100 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK3\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK3 1 CLK PIN_9 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_9; Fanout = 4; CLK Node = 'CLK3'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK3 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 568 360 528 584 "CLK3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 6.100 ns c10:inst42\|count\[3\] 2 REG LC7_A21 3 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'c10:inst42\|count\[3\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { CLK3 c10:inst42|count[3] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 55.74 % ) " "Info: Total cell delay = 3.400 ns ( 55.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 44.26 % ) " "Info: Total interconnect delay = 2.700 ns ( 44.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[3] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK3 source 6.100 ns - Longest register " "Info: - Longest clock path from clock \"CLK3\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CLK3 1 CLK PIN_9 4 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_9; Fanout = 4; CLK Node = 'CLK3'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK3 } "NODE_NAME" } } { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 568 360 528 584 "CLK3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 6.100 ns c10:inst42\|count\[0\] 2 REG LC6_A21 5 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC6_A21; Fanout = 5; REG Node = 'c10:inst42\|count\[0\]'" { } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { CLK3 c10:inst42|count[0] } "NODE_NAME" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 55.74 % ) " "Info: Total cell delay = 3.400 ns ( 55.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 44.26 % ) " "Info: Total interconnect delay = 2.700 ns ( 44.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[0] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[3] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[0] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { c10:inst42|count[0] c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.700 ns" { c10:inst42|count[0] {} c10:inst42|count[3] {} } { 0.000ns 0.200ns } { 0.000ns 1.500ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[3] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CLK3 c10:inst42|count[0] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { CLK3 {} CLK3~out {} c10:inst42|count[0] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.400ns 0.000ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c10:inst42|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c10:inst42|count[3] {} } { } { } "" } } { "c10.vhd" "" { Text "F:/FPGA/newszz/c10.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
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