prev_cmp_block.tan.qmsg

基于FPGA的多功能电子时钟的设计很经典的哦

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 992 1504 1672 1008 "CLK" "" } { 1240 1730 1768 1260 "CLK" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK2 " "Info: Assuming node \"CLK2\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 432 360 528 448 "CLK2" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK4 " "Info: Assuming node \"CLK4\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 704 360 528 720 "CLK4" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK4" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node \"CLK1\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 288 360 528 304 "CLK1" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK3 " "Info: Assuming node \"CLK3\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 568 360 528 584 "CLK3" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK6 " "Info: Assuming node \"CLK6\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 1104 360 528 1120 "CLK6" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK6" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK5 " "Info: Assuming node \"CLK5\" is an undefined clock" {  } { { "Block.bdf" "" { Schematic "F:/FPGA/newszz/Block.bdf" { { 840 360 528 856 "CLK5" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK5" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}