block.map.summary

来自「基于FPGA的多功能电子时钟的设计很经典的哦」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Mon Jun 16 16:48:20 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : Block
Top-level Entity Name : Block
Family : ACEX1K
Total logic elements : 141
Total pins : 47
Total memory bits : 0
Total PLLs : 0