decoder7.vhd

来自「基于FPGA的多功能电子时钟的设计很经典的哦」· VHDL 代码 · 共 24 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder7 is
Port (din:in std_logic_vector(3 downto 0 );   --四位二进制码输入
dout:out std_logic_vector(3 downto 0) );  --输出LED七段码，显示码对应gfedcba
end decoder7;
architecture Behavioral of decoder7 is
begin
process(din)
begin
case din is
when "0000" => dout<="0001";--1
when "0001" => dout<="0010";--2
when "0010" => dout<="0011";--3
when "0011" => dout<="0100";--4
when "0100" => dout<="0101";--5
when "0101" => dout<="0110";--6
when "0110" => dout<="1000";--8
when others => dout<="0000";
end case;
end process;
end Behavioral;