block.map.rpt

基于FPGA的多功能电子时钟的设计很经典的哦

; CBXI_PARAMETER         ; NOTHING           ; Untyped                                                 ;
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon Jun 16 16:48:16 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Block -c Block
Info: Found 1 design units, including 1 entities, in source file Block.bdf
    Info: Found entity 1: Block
Info: Found 2 design units, including 1 entities, in source file clk_div.vhd
    Info: Found design unit 1: clk_div-one
    Info: Found entity 1: clk_div
Info: Found 2 design units, including 1 entities, in source file class.vhd
    Info: Found design unit 1: class-one
    Info: Found entity 1: class
Info: Elaborating entity "Block" for the top level hierarchy
Info: Elaborating entity "class" for hierarchy "class:inst27"
Warning (10631): VHDL Process Statement warning at class.vhd(9): inferring latch(es) for signal or variable "b", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "b" at class.vhd(9)
Warning: Using design file decoder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: decoder-Behavioral
    Info: Found entity 1: decoder
Info: Elaborating entity "decoder" for hierarchy "decoder:inst7"
Warning: Using design file counter10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter10-Behavioral
    Info: Found entity 1: counter10
Info: Elaborating entity "counter10" for hierarchy "counter10:inst"
Warning (10492): VHDL Process Statement warning at counter10.vhd(17): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at counter10.vhd(28): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "clk_div" for hierarchy "clk_div:inst22"
Warning: Using design file c10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: c10-Behavioral
    Info: Found entity 1: c10
Info: Elaborating entity "c10" for hierarchy "c10:inst40"
Warning (10492): VHDL Process Statement warning at c10.vhd(20): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file counter6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter6-Behavioral
    Info: Found entity 1: counter6
Info: Elaborating entity "counter6" for hierarchy "counter6:inst1"
Warning (10492): VHDL Process Statement warning at counter6.vhd(18): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at counter6.vhd(29): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file c6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: c6-Behavioral
    Info: Found entity 1: c6
Info: Elaborating entity "c6" for hierarchy "c6:inst41"
Warning (10492): VHDL Process Statement warning at c6.vhd(20): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file counter24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter24-Behavioral
    Info: Found entity 1: counter24
Info: Elaborating entity "counter24" for hierarchy "counter24:inst5"
Warning (10492): VHDL Process Statement warning at counter24.vhd(17): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at counter24.vhd(33): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file c24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: c24-Behavioral
    Info: Found entity 1: c24
Info: Elaborating entity "c24" for hierarchy "c24:inst4"
Warning (10492): VHDL Process Statement warning at c24.vhd(24): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file decoder7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: decoder7-Behavioral
    Info: Found entity 1: decoder7
Info: Elaborating entity "decoder7" for hierarchy "decoder7:inst13"
Warning: Using design file counter7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter7-Behavioral
    Info: Found entity 1: counter7
Info: Elaborating entity "counter7" for hierarchy "counter7:inst6"
Warning (10492): VHDL Process Statement warning at counter7.vhd(17): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at counter7.vhd(25): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file c7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: c7-Behavioral
    Info: Found entity 1: c7
Info: Elaborating entity "c7" for hierarchy "c7:inst46"
Warning (10492): VHDL Process Statement warning at c7.vhd(20): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file zhongbai.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: zhongbai-one
    Info: Found entity 1: zhongbai
Info: Elaborating entity "zhongbai" for hierarchy "zhongbai:inst30"
Warning (14130): Reduced register "c24:inst4|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst4|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "counter24:inst5|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "counter24:inst5|count[6]" with stuck data_in port to stuck value GND
Info: Inferred 4 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter24:inst5|count[0]~17"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "c24:inst4|count[0]~17"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "clk_div:inst22|count[0]~14"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "clk_div:inst22|\process2:count[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../../quartusii/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "counter24:inst5|lpm_counter:count_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../../quartusii/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "counter24:inst5|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "counter24:inst5|lpm_counter:count_rtl_0"
Info: Instantiated megafunction "counter24:inst5|lpm_counter:count_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "c24:inst4|lpm_counter:count_rtl_1"
Info: Elaborated megafunction instantiation "c24:inst4|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "c24:inst4|lpm_counter:count_rtl_1"
Info: Instantiated megafunction "c24:inst4|lpm_counter:count_rtl_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "clk_div:inst22|lpm_counter:count_rtl_2"
Info: Elaborated megafunction instantiation "clk_div:inst22|lpm_counter:count_rtl_2|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "clk_div:inst22|lpm_counter:count_rtl_2"
Info: Instantiated megafunction "clk_div:inst22|lpm_counter:count_rtl_2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "9"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "clk_div:inst22|lpm_counter:\process2:count[0]_rtl_3"
Info: Elaborated megafunction instantiation "clk_div:inst22|lpm_counter:\process2:count[0]_rtl_3|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "clk_div:inst22|lpm_counter:\process2:count[0]_rtl_3"
Info: Instantiated megafunction "clk_div:inst22|lpm_counter:\process2:count[0]_rtl_3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "hourl[3]" stuck at GND
    Warning (13410): Pin "hourl[2]" stuck at GND
Info: Implemented 188 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 38 output pins
    Info: Implemented 141 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Mon Jun 16 16:48:20 2008
    Info: Elapsed time: 00:00:04