block.fit.summary

基于FPGA的多功能电子时钟的设计很经典的哦

Fitter Status : Successful - Mon Jun 16 16:48:33 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : Block
Top-level Entity Name : Block
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Total logic elements : 142 / 4,992 ( 3 % )
Total pins : 47 / 147 ( 32 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0