block.tan.rpt

基于FPGA的多功能电子时钟的设计很经典的哦

; Worst-case tsu               ; N/A   ; None          ; 3.200 ns                                       ; RST1                                                                        ; zhongbai:inst30|cnt[2]                                                      ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 48.700 ns                                      ; counter7:inst6|count[0]                                                     ; date[3]                                                                     ; CLK        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 22.400 ns                                      ; CLK                                                                         ; alart_1                                                                     ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.600 ns                                      ; RST1                                                                        ; zhongbai:inst30|cnt[2]                                                      ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 104.17 MHz ( period = 9.600 ns )               ; counter24:inst5|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; counter24:inst5|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK        ; CLK      ; 0            ;
; Clock Setup: 'CLK5'          ; N/A   ; None          ; 128.21 MHz ( period = 7.800 ns )               ; c24:inst4|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[3]       ; c24:inst4|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[2]       ; CLK5       ; CLK5     ; 0            ;
; Clock Setup: 'CLK6'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; c7:inst46|count[1]                                                          ; c7:inst46|count[3]                                                          ; CLK6       ; CLK6     ; 0            ;
; Clock Setup: 'CLK3'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; c10:inst42|count[0]                                                         ; c10:inst42|count[1]                                                         ; CLK3       ; CLK3     ; 0            ;
; Clock Setup: 'CLK1'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; c10:inst40|count[0]                                                         ; c10:inst40|count[1]                                                         ; CLK1       ; CLK1     ; 0            ;
; Clock Setup: 'CLK4'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; c6:inst43|count[1]                                                          ; c6:inst43|count[3]                                                          ; CLK4       ; CLK4     ; 0            ;
; Clock Setup: 'CLK2'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; c6:inst41|count[1]                                                          ; c6:inst41|count[3]                                                          ; CLK2       ; CLK2     ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                             ;                                                                             ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1K100QC208-3     ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK2            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK4            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;