reg32bit.vhd

来自「32位寄存器的VHDL的原代码下载,COOLCOOLCOOL」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic (n : natural := 32);
port (D : in std_logic_vector(31 downto 0);
Clock, Reset, Enable : in std_logic;
Q : out std_logic_vector(31 downto 0));
end entity reg;
architecture behavioural of reg is
begin
p0: process (Clock, Reset) is
begin
if (Reset = '0') then
Q <= (others => '0');
elsif rising_edge(Clock) then
if Enable = '1' then
Q <= D;
end if;
end if;
end process p0;
end architecture behavioural;