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-- Copyright (C) 1991-2003 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 3.0 Build 220 07/30/2003 Service Pack 1 SJ Full Version"
-- DATE "09/23/2003 14:35:40"
--
-- Device: Altera EP1S25F780C5 Package FBGA780
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL output from Quartus II) only
--
LIBRARY IEEE, stratix;
USE IEEE.std_logic_1164.all;
USE stratix.stratix_components.all;
ENTITY top IS
PORT (
RESET_N : IN std_logic;
clk : IN std_logic;
ADDR : IN std_logic_vector(16 DOWNTO 0);
RD_WR_N : IN std_logic;
ADDR_ADV_LD_N : IN std_logic;
DM : IN std_logic_vector(3 DOWNTO 0);
DATA_IN : IN std_logic_vector(35 DOWNTO 0);
DQ : INOUT std_logic_vector(35 DOWNTO 0);
DATA_OUT : OUT std_logic_vector(35 DOWNTO 0);
SA : OUT std_logic_vector(16 DOWNTO 0);
RW_N : OUT std_logic;
ADV_LD_N : OUT std_logic;
BW_N : OUT std_logic_vector(3 DOWNTO 0)
);
END top;
ARCHITECTURE structure OF top IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL ww_RESET_N : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_ADDR : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_RD_WR_N : std_logic;
SIGNAL ww_ADDR_ADV_LD_N : std_logic;
SIGNAL ww_DM : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_DATA_IN : std_logic_vector(35 DOWNTO 0);
SIGNAL ww_DATA_OUT : std_logic_vector(35 DOWNTO 0);
SIGNAL ww_SA : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_RW_N : std_logic;
SIGNAL ww_ADV_LD_N : std_logic;
SIGNAL ww_BW_N : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_PLL1_inst_aaltpll_component_apll_inclk : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_PLL1_inst_aaltpll_component_apll_clk : std_logic_vector(5 DOWNTO 0);
SIGNAL PLL1_inst_aaltpll_component_apll_aCLK1 : std_logic;
SIGNAL PLL1_inst_aaltpll_component_apll_aCLK2 : std_logic;
SIGNAL PLL1_inst_aaltpll_component_apll_aCLK3 : std_logic;
SIGNAL PLL1_inst_aaltpll_component_apll_aCLK4 : std_logic;
SIGNAL PLL1_inst_aaltpll_component_apll_aCLK5 : std_logic;
SIGNAL RESET_N_apadio : std_logic;
SIGNAL clk_apadio : std_logic;
SIGNAL ADDR_a16_a_apadio : std_logic;
SIGNAL ADDR_a15_a_apadio : std_logic;
SIGNAL ADDR_a14_a_apadio : std_logic;
SIGNAL ADDR_a13_a_apadio : std_logic;
SIGNAL ADDR_a12_a_apadio : std_logic;
SIGNAL ADDR_a11_a_apadio : std_logic;
SIGNAL ADDR_a10_a_apadio : std_logic;
SIGNAL ADDR_a9_a_apadio : std_logic;
SIGNAL ADDR_a8_a_apadio : std_logic;
SIGNAL ADDR_a7_a_apadio : std_logic;
SIGNAL ADDR_a6_a_apadio : std_logic;
SIGNAL ADDR_a5_a_apadio : std_logic;
SIGNAL ADDR_a4_a_apadio : std_logic;
SIGNAL ADDR_a3_a_apadio : std_logic;
SIGNAL ADDR_a2_a_apadio : std_logic;
SIGNAL ADDR_a1_a_apadio : std_logic;
SIGNAL ADDR_a0_a_apadio : std_logic;
SIGNAL RD_WR_N_apadio : std_logic;
SIGNAL ADDR_ADV_LD_N_apadio : std_logic;
SIGNAL DM_a3_a_apadio : std_logic;
SIGNAL DM_a2_a_apadio : std_logic;
SIGNAL DM_a1_a_apadio : std_logic;
SIGNAL DM_a0_a_apadio : std_logic;
SIGNAL DATA_IN_a35_a_apadio : std_logic;
SIGNAL DATA_IN_a34_a_apadio : std_logic;
SIGNAL DATA_IN_a33_a_apadio : std_logic;
SIGNAL DATA_IN_a32_a_apadio : std_logic;
SIGNAL DATA_IN_a31_a_apadio : std_logic;
SIGNAL DATA_IN_a30_a_apadio : std_logic;
SIGNAL DATA_IN_a29_a_apadio : std_logic;
SIGNAL DATA_IN_a28_a_apadio : std_logic;
SIGNAL DATA_IN_a27_a_apadio : std_logic;
SIGNAL DATA_IN_a26_a_apadio : std_logic;
SIGNAL DATA_IN_a25_a_apadio : std_logic;
SIGNAL DATA_IN_a24_a_apadio : std_logic;
SIGNAL DATA_IN_a23_a_apadio : std_logic;
SIGNAL DATA_IN_a22_a_apadio : std_logic;
SIGNAL DATA_IN_a21_a_apadio : std_logic;
SIGNAL DATA_IN_a20_a_apadio : std_logic;
SIGNAL DATA_IN_a19_a_apadio : std_logic;
SIGNAL DATA_IN_a18_a_apadio : std_logic;
SIGNAL DATA_IN_a17_a_apadio : std_logic;
SIGNAL DATA_IN_a16_a_apadio : std_logic;
SIGNAL DATA_IN_a15_a_apadio : std_logic;
SIGNAL DATA_IN_a14_a_apadio : std_logic;
SIGNAL DATA_IN_a13_a_apadio : std_logic;
SIGNAL DATA_IN_a12_a_apadio : std_logic;
SIGNAL DATA_IN_a11_a_apadio : std_logic;
SIGNAL DATA_IN_a10_a_apadio : std_logic;
SIGNAL DATA_IN_a9_a_apadio : std_logic;
SIGNAL DATA_IN_a8_a_apadio : std_logic;
SIGNAL DATA_IN_a7_a_apadio : std_logic;
SIGNAL DATA_IN_a6_a_apadio : std_logic;
SIGNAL DATA_IN_a5_a_apadio : std_logic;
SIGNAL DATA_IN_a4_a_apadio : std_logic;
SIGNAL DATA_IN_a3_a_apadio : std_logic;
SIGNAL DATA_IN_a2_a_apadio : std_logic;
SIGNAL DATA_IN_a1_a_apadio : std_logic;
SIGNAL DATA_IN_a0_a_apadio : std_logic;
SIGNAL DATA_OUT_a35_a_apadio : std_logic;
SIGNAL DATA_OUT_a34_a_apadio : std_logic;
SIGNAL DATA_OUT_a33_a_apadio : std_logic;
SIGNAL DATA_OUT_a32_a_apadio : std_logic;
SIGNAL DATA_OUT_a31_a_apadio : std_logic;
SIGNAL DATA_OUT_a30_a_apadio : std_logic;
SIGNAL DATA_OUT_a29_a_apadio : std_logic;
SIGNAL DATA_OUT_a28_a_apadio : std_logic;
SIGNAL DATA_OUT_a27_a_apadio : std_logic;
SIGNAL DATA_OUT_a26_a_apadio : std_logic;
SIGNAL DATA_OUT_a25_a_apadio : std_logic;
SIGNAL DATA_OUT_a24_a_apadio : std_logic;
SIGNAL DATA_OUT_a23_a_apadio : std_logic;
SIGNAL DATA_OUT_a22_a_apadio : std_logic;
SIGNAL DATA_OUT_a21_a_apadio : std_logic;
SIGNAL DATA_OUT_a20_a_apadio : std_logic;
SIGNAL DATA_OUT_a19_a_apadio : std_logic;
SIGNAL DATA_OUT_a18_a_apadio : std_logic;
SIGNAL DATA_OUT_a17_a_apadio : std_logic;
SIGNAL DATA_OUT_a16_a_apadio : std_logic;
SIGNAL DATA_OUT_a15_a_apadio : std_logic;
SIGNAL DATA_OUT_a14_a_apadio : std_logic;
SIGNAL DATA_OUT_a13_a_apadio : std_logic;
SIGNAL DATA_OUT_a12_a_apadio : std_logic;
SIGNAL DATA_OUT_a11_a_apadio : std_logic;
SIGNAL DATA_OUT_a10_a_apadio : std_logic;
SIGNAL DATA_OUT_a9_a_apadio : std_logic;
SIGNAL DATA_OUT_a8_a_apadio : std_logic;
SIGNAL DATA_OUT_a7_a_apadio : std_logic;
SIGNAL DATA_OUT_a6_a_apadio : std_logic;
SIGNAL DATA_OUT_a5_a_apadio : std_logic;
SIGNAL DATA_OUT_a4_a_apadio : std_logic;
SIGNAL DATA_OUT_a3_a_apadio : std_logic;
SIGNAL DATA_OUT_a2_a_apadio : std_logic;
SIGNAL DATA_OUT_a1_a_apadio : std_logic;
SIGNAL DATA_OUT_a0_a_apadio : std_logic;
SIGNAL SA_a16_a_apadio : std_logic;
SIGNAL SA_a15_a_apadio : std_logic;
SIGNAL SA_a14_a_apadio : std_logic;
SIGNAL SA_a13_a_apadio : std_logic;
SIGNAL SA_a12_a_apadio : std_logic;
SIGNAL SA_a11_a_apadio : std_logic;
SIGNAL SA_a10_a_apadio : std_logic;
SIGNAL SA_a9_a_apadio : std_logic;
SIGNAL SA_a8_a_apadio : std_logic;
SIGNAL SA_a7_a_apadio : std_logic;
SIGNAL SA_a6_a_apadio : std_logic;
SIGNAL SA_a5_a_apadio : std_logic;
SIGNAL SA_a4_a_apadio : std_logic;
SIGNAL SA_a3_a_apadio : std_logic;
SIGNAL SA_a2_a_apadio : std_logic;
SIGNAL SA_a1_a_apadio : std_logic;
SIGNAL SA_a0_a_apadio : std_logic;
SIGNAL DQ_a35_a_apadio : std_logic;
SIGNAL DQ_a34_a_apadio : std_logic;
SIGNAL DQ_a33_a_apadio : std_logic;
SIGNAL DQ_a32_a_apadio : std_logic;
SIGNAL DQ_a31_a_apadio : std_logic;
SIGNAL DQ_a30_a_apadio : std_logic;
SIGNAL DQ_a29_a_apadio : std_logic;
SIGNAL DQ_a28_a_apadio : std_logic;
SIGNAL DQ_a27_a_apadio : std_logic;
SIGNAL DQ_a26_a_apadio : std_logic;
SIGNAL DQ_a25_a_apadio : std_logic;
SIGNAL DQ_a24_a_apadio : std_logic;
SIGNAL DQ_a23_a_apadio : std_logic;
SIGNAL DQ_a22_a_apadio : std_logic;
SIGNAL DQ_a21_a_apadio : std_logic;
SIGNAL DQ_a20_a_apadio : std_logic;
SIGNAL DQ_a19_a_apadio : std_logic;
SIGNAL DQ_a18_a_apadio : std_logic;
SIGNAL DQ_a17_a_apadio : std_logic;
SIGNAL DQ_a16_a_apadio : std_logic;
SIGNAL DQ_a15_a_apadio : std_logic;
SIGNAL DQ_a14_a_apadio : std_logic;
SIGNAL DQ_a13_a_apadio : std_logic;
SIGNAL DQ_a12_a_apadio : std_logic;
SIGNAL DQ_a11_a_apadio : std_logic;
SIGNAL DQ_a10_a_apadio : std_logic;
SIGNAL DQ_a9_a_apadio : std_logic;
SIGNAL DQ_a8_a_apadio : std_logic;
SIGNAL DQ_a7_a_apadio : std_logic;
SIGNAL DQ_a6_a_apadio : std_logic;
SIGNAL DQ_a5_a_apadio : std_logic;
SIGNAL DQ_a4_a_apadio : std_logic;
SIGNAL DQ_a3_a_apadio : std_logic;
SIGNAL DQ_a2_a_apadio : std_logic;
SIGNAL DQ_a1_a_apadio : std_logic;
SIGNAL DQ_a0_a_apadio : std_logic;
SIGNAL RW_N_apadio : std_logic;
SIGNAL ADV_LD_N_apadio : std_logic;
SIGNAL BW_N_a3_a_apadio : std_logic;
SIGNAL BW_N_a2_a_apadio : std_logic;
SIGNAL BW_N_a1_a_apadio : std_logic;
SIGNAL BW_N_a0_a_apadio : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a34_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a28_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a23_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a22_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a0_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a26_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a31_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a14_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a16_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a11_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a9_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a35_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a10_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a21_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a6_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a3_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a33_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a30_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a24_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a2_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a1_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a27_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a25_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a32_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a18_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a15_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a29_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a12_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a8_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a20_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a7_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a17_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a13_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a5_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a4_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a19_a_areg0 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL PLL1_inst_aaltpll_component_a_clk0 : std_logic;
SIGNAL DM_a2_a_acombout : std_logic;
SIGNAL RESET_N_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a2_a_areg0 : std_logic;
SIGNAL DM_a0_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a0_a_areg0 : std_logic;
SIGNAL DM_a3_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a3_a_areg0 : std_logic;
SIGNAL DM_a1_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a1_a_areg0 : std_logic;
SIGNAL DATA_IN_a34_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a34_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a34_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a34_a : std_logic;
SIGNAL RD_WR_N_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_ard_wr_n_reg_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a0_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a : std_logic;
SIGNAL DATA_IN_a28_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a28_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a28_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a28_a : std_logic;
SIGNAL DATA_IN_a23_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a23_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a23_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a23_a : std_logic;
SIGNAL DATA_IN_a22_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a22_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a22_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a22_a : std_logic;
SIGNAL DATA_IN_a0_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a0_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a0_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a0_a : std_logic;
SIGNAL DATA_IN_a26_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a26_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a26_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a26_a : std_logic;
SIGNAL DATA_IN_a31_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a31_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a31_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a31_a : std_logic;
SIGNAL DATA_IN_a14_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a14_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a14_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a14_a : std_logic;
SIGNAL DATA_IN_a16_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a16_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a16_a : std_logic;
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